Search Results for author: Andreas Grübl

Found 14 papers, 0 papers with code

Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

no code implementations15 Jan 2018 Kai Zoschke, Maurice Güttler, Lars Böttcher, Andreas Grübl, Dan Husmann, Johannes Schemmel, Karlheinz Meier, Oswin Ehrmann

Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system.

Robustness from structure: Inference with hierarchical spiking networks on analog neuromorphic hardware

no code implementations12 Mar 2017 Mihai A. Petrovici, Anna Schroeder, Oliver Breitwieser, Andreas Grübl, Johannes Schemmel, Karlheinz Meier

How spiking networks are able to perform probabilistic inference is an intriguing question, not only for understanding information processing in the brain, but also for transferring these computational principles to neuromorphic silicon circuits.

Demonstrating Advantages of Neuromorphic Computation: A Pilot Study

no code implementations8 Nov 2018 Timo Wunderlich, Akos F. Kungl, Eric Müller, Andreas Hartel, Yannik Stradmann, Syed Ahmed Aamir, Andreas Grübl, Arthur Heimbrecht, Korbinian Schreiber, David Stöckel, Christian Pehle, Sebastian Billaudelle, Gerd Kiene, Christian Mauch, Johannes Schemmel, Karlheinz Meier, Mihai A. Petrovici

Neuromorphic devices represent an attempt to mimic aspects of the brain's architecture and dynamics with the aim of replicating its hallmark functional capabilities in terms of computational power, robust learning and energy efficiency.

A VLSI Implementation of the Adaptive Exponential Integrate-and-Fire Neuron Model

no code implementations NeurIPS 2010 Sebastian Millner, Andreas Grübl, Karlheinz Meier, Johannes Schemmel, Marc-Olivier Schwartz

We describe an accelerated hardware neuron being capable of emulating the adap-tive exponential integrate-and-fire neuron model.

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

no code implementations25 Mar 2020 Andreas Grübl, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, Johannes Schemmel

This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65nm ASICs.

The Operating System of the Neuromorphic BrainScaleS-1 System

no code implementations30 Mar 2020 Eric Müller, Sebastian Schmitt, Christian Mauch, Sebastian Billaudelle, Andreas Grübl, Maurice Güttler, Dan Husmann, Joscha Ilmberger, Sebastian Jeltsch, Jakob Kaiser, Johann Klähn, Mitja Kleider, Christoph Koke, José Montes, Paul Müller, Johannes Partzsch, Felix Passenberg, Hartmut Schmidt, Bernhard Vogginger, Jonas Weidner, Christian Mayr, Johannes Schemmel

We present operation and development methodologies implemented for the BrainScaleS-1 neuromorphic architecture and walk through the individual components of BrainScaleS OS constituting the software stack for BrainScaleS-1 platform operation.

Surrogate gradients for analog neuromorphic computing

no code implementations12 Jun 2020 Benjamin Cramer, Sebastian Billaudelle, Simeon Kanya, Aron Leibfried, Andreas Grübl, Vitali Karasenko, Christian Pehle, Korbinian Schreiber, Yannik Stradmann, Johannes Weis, Johannes Schemmel, Friedemann Zenke

To rapidly process temporal information at a low metabolic cost, biological neurons integrate inputs as an analog sum but communicate with spikes, binary events in time.

BrainScaleS Large Scale Spike Communication using Extoll

no code implementations30 Nov 2021 Tobias Thommes, Niels Buwen, Andreas Grübl, Eric Müller, Ulrich Brüning, Johannes Schemmel

The BrainScaleS Neuromorphic Computing System is currently connected to a compute cluster via Gigabit-Ethernet network technology.

Demonstrating BrainScaleS-2 Inter-Chip Pulse-Communication using EXTOLL

no code implementations24 Feb 2022 Tobias Thommes, Sven Bordukat, Andreas Grübl, Vitali Karasenko, Eric Müller, Johannes Schemmel

The BrainScaleS-2 (BSS-2) Neuromorphic Computing System currently consists of multiple single-chip setups, which are connected to a compute cluster via Gigabit-Ethernet network technology.

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