Search Results for author:
Found 5 papers, 2 papers with code
VeriGen: A Large Language Model for Verilog Code Generation
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems.
FLAG: Finding Line Anomalies (in code) with Generative AI
In this work, we explore the features that help LLMs in this classification and evaluate the performance of FLAG on known bugs.
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors.
Examining Zero-Shot Vulnerability Repair with Large Language Models
We perform a large scale study of five commercially available, black-box, "off-the-shelf" LLMs, as well as an open-source model and our own locally-trained model, on a mix of synthetic, hand-crafted, and real-world security bug scenarios.
Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions
The most notable of these comes in the form of the first self-described `AI pair programmer', GitHub Copilot, a language model trained over open-source GitHub code.
