Search Results for author:
Found 11 papers, 3 papers with code
Accelerator-aware Neural Network Design using AutoML
While neural network hardware accelerators provide a substantial amount of raw compute throughput, the models deployed on them must be co-designed for the underlying hardware architecture to obtain the optimal system performance.
Hardware Aware Neural Architecture Search
Image Classification
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MobileDets: Searching for Object Detection Architectures for Mobile Accelerators
By incorporating regular convolutions in the search space and directly optimizing the network architectures for object detection, we obtain a family of object detection models, MobileDets, that achieve state-of-the-art results across mobile accelerators.
Discovering Multi-Hardware Mobile Models via Architecture Search
Hardware-aware neural architecture designs have been predominantly focusing on optimizing model performance on single hardware and model development complexity, where another important factor, model deployment complexity, has been largely ignored.
NAHAS: Neural Architecture and Hardware Accelerator Search
In this paper, we study the importance of co-designing neural architectures and hardware accelerators.
Apollo: Transferable Architecture Exploration
We further show that by transferring knowledge between target architectures with different design constraints, Apollo is able to find optimal configurations faster and often with better objective value (up to 25% improvements).
Rethinking Co-design of Neural Architectures and Hardware Accelerators
In our work, we target the optimization of hardware and software configurations on an industry-standard edge accelerator.
An Evaluation of Edge TPU Accelerators for Convolutional Neural Networks
Then, we extensively evaluate three classes of Edge TPUs, covering different computing ecosystems, that are either currently deployed in Google products or are the product pipeline, across 423K unique convolutional neural networks.
Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models
We comprehensively study the characteristics of each NN layer in all of the Google edge models, and find that these shortcomings arise from the one-size-fits-all approach of the accelerator, as there is a high amount of heterogeneity in key layer characteristics both across different models and across different layers in the same model.
Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks
To understand how edge ML accelerators perform, we characterize the performance of a commercial Google Edge TPU, using 24 Google edge NN models (which span a wide range of NN model types) and analyzing each NN layer within each model.
Searching for Efficient Neural Architectures for On-Device ML on Edge TPUs
On-device ML accelerators are becoming a standard in modern mobile system-on-chips (SoC).
MobileNetV4 - Universal Models for the Mobile Ecosystem
We present the latest generation of MobileNets, known as MobileNetV4 (MNv4), featuring universally efficient architecture designs for mobile devices.
