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Found 20 papers, 7 papers with code
Stream-Based Monitoring of Algorithmic Fairness
Concretely, we present a principled way to formalize algorithmic fairness over temporal data streams in the specification language RTLola and demonstrate the efficacy of this approach on a number of benchmarks.
Non-Deterministic Planning for Hyperproperty Verification
We show that for large fragments of HyperLTL, the resulting planning instance corresponds to a classical, FOND, or POND planning problem.
Monitoring Second-Order Hyperproperties
For the parallel model, we show that the monitoring of the second-order hyperproperties of Hyper$^2$LTL$_f$ can be reduced to monitoring first-order hyperproperties.
Hyper Strategy Logic
In this paper, we present Hyper Strategy Logic (HyperSL), a strategy logic where the outcome of multiple strategy profiles can be compared w. r. t.
Learning Better Representations From Less Data For Propositional Satisfiability
By combining certificate-driven training and expert iteration, our model learns better representations than models trained for classification only, with a much higher data efficiency -- requiring orders of magnitude less training data.
On Alternating-Time Temporal Logic, Hyperproperties, and Strategy Sharing
However, while ATL$^*$ can reason about the strategic ability of agents (e. g., some coalition $A$ can ensure that a goal is reached eventually), we cannot compare multiple strategic interactions, nor can we require multiple agents to follow the same strategy.
Counterfactuals Modulo Temporal Logics
Lewis' theory of counterfactuals is the foundation of many contemporary notions of causality.
Iterative Circuit Repair Against Formal Specifications
We propose a separated hierarchical Transformer for multimodal representation learning of the formal specification and the circuit.
Formal Specifications from Natural Language
We study the generalization abilities of language models when translating natural language into formal specifications with complex semantics.
Attention Flows for General Transformers
In this paper, we study the computation of how much an input token in a Transformer model influences its prediction.
Neural Circuit Synthesis from Specification Patterns
We train hierarchical Transformers on the task of synthesizing hardware circuits directly out of high-level logical specifications in linear-time temporal logic (LTL).
Efficient Monitoring of Hyperproperties using Prefix Trees
Hyperproperties, such as non-interference and observational determinism, relate multiple computation traces with each other and are thus not monitorable by tools that consider computations in isolation.
Logic in Computer Science
Realizing Omega-regular Hyperproperties
We furthermore studied the realizability problem of HyperQPTL.
Logic in Computer Science
Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications
Syntroids is a space shooter arcade game realized on an FPGA, where the control flow architecture has been completely specified in Temporal Stream Logic (TSL) and implemented using reactive synthesis.
Hardware Architecture
Linear-time Temporal Logic with Team Semantics: Expressivity and Complexity
We study the expressivity and complexity of model checking linear temporal logic with team semantics (TeamLTL).
Logic in Computer Science Computational Complexity F.4.1; D.2.4
Teaching Temporal Logics to Neural Networks
We study two fundamental questions in neuro-symbolic computing: can deep learning tackle challenging problems in logics end-to-end, and can neural networks learn the semantics of logics.
Proceedings 3rd Workshop on formal reasoning about Causation, Responsibility, and Explanations in Science and Technology
A further objective is to link to the foundations of causal reasoning in the philosophy of sciences and to causal reasoning performed in other areas of computer science, engineering, and beyond.
Synthesizing Skeletons for Reactive Systems
This information is represented in the form of a labeled transition system, which we call skeleton.
Temporal Stream Logic: Synthesis beyond the Bools
On the other hand, however, synthesis from TSL is scalable, because it is independent of the complexity of the handled data.
Logic in Computer Science
Temporal Logics for Hyperproperties
Standard temporal logics such as LTL, CTL, and CTL* can refer only to a single path at a time, hence cannot express many hyperproperties of interest.
Logic in Computer Science
