Search Results for author:
Found 45 papers, 21 papers with code
CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes
We demonstrate CSRNet on four datasets (ShanghaiTech dataset, the UCF_CC_50 dataset, the WorldEXPO'10 dataset, and the UCSD dataset) and we deliver the state-of-the-art performance.
Ranked #3 on
Crowd Counting
on Venice
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Deep Convolutional Neural Networks have become a Swiss knife in solving critical artificial intelligence tasks.
Improved ASR for Under-Resourced Languages Through Multi-Task Learning with Acoustic Landmarks
Furui first demonstrated that the identity of both consonant and vowel can be perceived from the C-V transition; later, Stevens proposed that acoustic landmarks are the primary cues for speech perception, and that steady-state regions are secondary or supplemental.
Automatic Speech Recognition
Automatic Speech Recognition (ASR)
+2
Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes.
When CTC Training Meets Acoustic Landmarks
In this paper, the convergence properties of CTC are improved by incorporating acoustic landmarks.
SiamVGG: Visual Tracking using Deeper Siamese Networks
It combines a Convolutional Neural Network (CNN) backbone and a cross-correlation operator, and takes advantage of the features from exemplary images for more accurate object tracking.
Ranked #1 on
Visual Object Tracking
on OTB-50
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge
While embedded FPGAs are attractive platforms for DNN acceleration on edge-devices due to their low latency and high energy efficiency, the scarcity of resources of edge-scale FPGA devices also makes it challenging for DNN deployment.
A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices
Developing deep learning models for resource-constrained Internet-of-Things (IoT) devices is challenging, as it is difficult to achieve both good quality of results (QoR), such as DNN model inference accuracy, and quality of service (QoS), such as inference latency, throughput, and power consumption.
SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection
Developing artificial intelligence (AI) at the edge is always challenging, since edge devices have limited computation capability and memory resources but need to meet demanding requirements, such as real-time processing, high throughput performance, and high inference accuracy.
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems
Object detection and tracking are challenging tasks for resource-constrained embedded systems.
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
The rapidly growing demands for powerful AI algorithms in many application domains have motivated massive investment in both high-quality deep neural network (DNN) models and high-efficiency implementations.
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
Specifically, AutoDNNchip consists of two integrated enablers: (1) a Chip Predictor, built on top of a graph-based accelerator representation, which can accurately and efficiently predict a DNN accelerator's energy, throughput, and area based on the DNN model parameters, hardware configuration, technology-based IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selection, block configuration, resource balancing, etc.
Compressing Large-Scale Transformer-Based Models: A Case Study on BERT
Pre-trained Transformer-based models have achieved state-of-the-art performance for various Natural Language Processing (NLP) tasks.
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
To speedup Deep Neural Networks (DNN) accelerator design and enable effective implementation, we propose HybridDNN, a framework for building high-performance hybrid DNN accelerators and delivering FPGA-based hardware implementations.
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
We formulate the co-search problem by fusing DNN search variables and hardware implementation variables into one solution space, and maximize both algorithm accuracy and hardware implementation quality.
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization
Quantization has been proven to be an effective method for reducing the computing and/or storage cost of DNNs.
Comprehensive assessment of error correction methods for high-throughput sequencing data
We also present a compilation of sequencing datasets for Illumina, PacBio and ONT platforms that present challenging scenarios for error-correction tools.
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices
High quality AI solutions require joint optimization of AI algorithms, such as deep neural networks (DNNs), and their hardware accelerators.
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
We design an efficient FPGA-based accelerator for our novel BNN model that supports the fractional activations.
Improving Random-Sampling Neural Architecture Search by Evolving the Proxy Search Space
This raises the question of whether we can find an effective proxy search space (PS) that is only a small subset of GS to dramatically improve RandomNAS’s search efficiency while at the same time keeping a good correlation for the top-performing architectures.
TwinDNN: A Tale of Two Deep Neural Networks
This is the first work that considers using a highly compressed DNN along with the original DNN in parallel to improve latency significantly while effectively maintaining the original model accuracy.
PyTorch-Direct: Enabling GPU Centric Data Access for Very Large Graph Neural Network Training with Irregular Accesses
While this process accounts for a significant portion of the training time, we find existing GNN implementations using popular deep neural network (DNN) libraries such as PyTorch are limited to a CPU-centric approach for the entire data preparation step.
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture
In this work, we propose a novel GPU-oriented data communication approach for GCN training, where GPU threads directly access sparse features in host memory through zero-copy accesses without much CPU help.
F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding
Creating virtual avatars with realistic rendering is one of the most essential and challenging tasks to provide highly immersive virtual reality (VR) experiences.
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design
Artificial intelligence (AI) technologies have dramatically advanced in recent years, resulting in revolutionary changes in people's lives.
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems
We formulate the MMMT model and heterogeneous hardware implementation co-design as a differentiable optimization problem, with the objective of improving the solution quality and reducing the overall power consumption and critical path latency.
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
We implement our proposed accelerator on multiple FPGAs, which outperforms the state-of-the-art designs in terms of both throughput and DSP efficiency.
Generic Neural Architecture Search via Regression
Such a self-supervised regression task can effectively evaluate the intrinsic power of an architecture to capture and transform the input signal patterns, and allow more sufficient usage of training samples.
Ranked #1 on
Neural Architecture Search
on NAS-Bench-101
(Spearman Correlation metric)
YOLO-ReT: Towards High Accuracy Real-time Object Detection on Edge GPUs
Performance of object detection models has been growing rapidly on two major fronts, model accuracy and efficiency.
EH-DNAS: End-to-End Hardware-aware Differentiable Neural Architecture Search
In this work, we propose End-to-end Hardware-aware DNAS (EH-DNAS), a seamless integration of end-to-end hardware benchmarking, and fully automated DNAS to deliver hardware-efficient deep neural networks on various platforms, including Edge GPUs, Edge TPUs, Mobile CPUs, and customized accelerators.
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Quantization for Convolutional Neural Network (CNN) has shown significant progress with the intention of reducing the cost of computation and storage with low-bitwidth data inputs.
AutoDistill: an End-to-End Framework to Explore and Distill Hardware-Efficient Language Models
By evaluating on SQuAD, a model found by AutoDistill achieves an 88. 4% F1 score with 22. 8M parameters, which reduces parameters by more than 62% while maintaining higher accuracy than DistillBERT, TinyBERT, and NAS-BERT.
Physics Community Needs, Tools, and Resources for Machine Learning
Machine learning (ML) is becoming an increasingly important component of cutting-edge physics research, but its computational requirements present significant challenges.
Compilation and Optimizations for Efficient Machine Learning on Embedded Systems
Deep Neural Networks (DNNs) have achieved great success in a variety of machine learning (ML) applications, delivering high-quality inferencing solutions in computer vision, natural language processing, and virtual reality, etc.
Chimera: A Hybrid Machine Learning Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis
However, with the high flexibility comes the difficulty in design and optimization.
ORB-based SLAM accelerator on SoC FPGA
Simultaneous Localization and Mapping (SLAM) is one of the main components of autonomous navigation systems.
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
In this study, we propose HiKonv, a unified solution that maximizes the throughput of convolution on a given underlying processing unit with low-bitwidth quantized data inputs through novel bit-wise management and parallel computation.
What Makes Convolutional Models Great on Long Sequence Modeling?
We focus on the structure of the convolution kernel and identify two critical but intuitive principles enjoyed by S4 that are sufficient to make up an effective global convolutional model: 1) The parameterization of the convolutional kernel needs to be efficient in the sense that the number of parameters should scale sub-linearly with sequence length.
Ranked #6 on
Long-range modeling
on LRA
Extensible Proxy for Efficient NAS
(2) Efficient proxies are not extensible to multi-modality downstream tasks.
Extensible and Efficient Proxy for Neural Architecture Search
We further propose a Discrete Proxy Search (DPS) method to find the optimized training settings for Eproxy with only a handful of benchmarked architectures on the target tasks.
Medusa: Simple LLM Inference Acceleration Framework with Multiple Decoding Heads
We present two levels of fine-tuning procedures for Medusa to meet the needs of different use cases: Medusa-1: Medusa is directly fine-tuned on top of a frozen backbone LLM, enabling lossless inference acceleration.
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS
This paper proposes ISDC, a novel feedback-guided iterative system of difference constraints (SDC) scheduling algorithm for high-level synthesis (HLS).
FedCore: Straggler-Free Federated Learning with Distributed Coresets
Federated learning (FL) is a machine learning paradigm that allows multiple clients to collaboratively train a shared model while keeping their data on-premise.
On the Surprising Efficacy of Distillation as an Alternative to Pre-Training Small Models
We observe that, when distilled on a task from a pre-trained teacher model, a small model can achieve or surpass the performance it would achieve if it was pre-trained then finetuned on that task.
SnapKV: LLM Knows What You are Looking for Before Generation
Specifically, SnapKV achieves a consistent decoding speed with a 3. 6x increase in generation speed and an 8. 2x enhancement in memory efficiency compared to baseline when processing inputs of 16K tokens.
