Search Results for author: H. -S. Philip Wong

Found 6 papers, 0 papers with code

Neural Network Compression for Noisy Storage Devices

no code implementations15 Feb 2021 Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H. -S. Philip Wong, Armin Alaghi

We propose a radically different approach that: (i) employs analog memories to maximize the capacity of each memory cell, and (ii) jointly optimizes model compression and physical storage to maximize memory utility.

Neural Network Compression

Hyperdimensional Computing Nanosystem

no code implementations23 Nov 2018 Abbas Rahimi, Tony F. Wu, Haitong Li, Jan M. Rabaey, H. -S. Philip Wong, Max M. Shulaker, Subhasish Mitra

By exploiting the unique properties of the underlying nanotechnologies, we show that HD computing, when implemented with monolithic 3D integration, can be up to 420X more energy-efficient while using 25X less area compared to traditional silicon CMOS implementations.

Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses

no code implementations27 Sep 2016 S. Burc Eryilmaz, Emre Neftci, Siddharth Joshi, Sang-Bum Kim, Matthew BrightSky, Hsiang-Lan Lung, Chung Lam, Gert Cauwenberghs, H. -S. Philip Wong

Current large scale implementations of deep learning and data mining require thousands of processors, massive amounts of off-chip memory, and consume gigajoules of energy.

Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures

no code implementations25 Dec 2015 Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H. -S. Philip Wong

This paper gives an overview of recent progress in the brain inspired computing field with a focus on implementation using emerging memories as electronic synapses.

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

no code implementations19 Jun 2014 Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Jeyasingh, Sang-Bum Kim, Matthew BrightSky, Chung Lam, H. -S. Philip Wong

Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements.

Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices

no code implementations29 May 2014 S. Burc Eryilmaz, Duygu Kuzum, Rakesh G. D. Jeyasingh, Sang-Bum Kim, Matthew BrightSky, Chung Lam, H. -S. Philip Wong

We demonstrate, in hardware, that 2-D crossbar arrays of phase change synaptic devices can achieve associative learning and perform pattern recognition.

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