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Found 22 papers, 2 papers with code
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing
Advancements in chip design and manufacturing have enabled the processing of complex tasks such as deep learning and natural language processing, paving the way for the development of artificial general intelligence (AGI).
Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks
To address this gap, the open-source VerilogEval benchmark was released in 2023, providing a consistent evaluation framework for LLMs on code completion tasks.
Differentiable Edge-based OPC
Optical proximity correction (OPC) is crucial for pushing the boundaries of semiconductor manufacturing and enabling the continued scaling of integrated circuits.
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors.
Code Less, Align More: Efficient LLM Fine-tuning for Code Generation with Data Pruning
We observe significant redundancies in synthetic training data generation, where our experiments demonstrate that benchmark performance can be largely preserved by training on only 10% of the data.
GOALPlace: Begin with the End in Mind
Co-optimizing placement with congestion is integral to achieving high-quality designs.
Large Language Model (LLM) for Standard Cell Layout Design Optimization
The state-of-the-art standard cell design automation framework is able to automatically design standard cell layouts in advanced nodes, but it is still struggling to generate highly competitive Performance-Power-Area (PPA) and routable cell layouts for complex sequential cell designs.
ILILT: Implicit Learning of Inverse Lithography Technologies
Lithography, transferring chip design masks to the silicon wafer, is the most important phase in modern semiconductor manufacturing flow.
Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance
This paper presents a comparative analysis of total cost of ownership (TCO) and performance between domain-adapted large language models (LLM) and state-of-the-art (SoTA) LLMs , with a particular emphasis on tasks related to coding assistance for chip design.
Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent
Exploding predictive AI has enabled fast yet effective evaluation and decision-making in modern chip physical design flows.
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Boolean algebraic manipulation is at the core of logic synthesis in Electronic Design Automation (EDA) design flow.
ChipNeMo: Domain-Adapted LLMs for Chip Design
ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design.
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains.
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
These synthetic mask images will augment the original limited training dataset used to finetune the lithography model for improved performance.
TAG: Learning Circuit Spatial Embedding From Layouts
Analog and mixed-signal (AMS) circuit designs still rely on human design expertise.
Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training
Machine learning techniques have been extensively studied for mask optimization problems, aiming at better mask printability, shorter turnaround time, better mask manufacturability, and so on.
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Lithography simulation is a critical step in VLSI design and optimization for manufacturability.
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
In this paper, we present GATSPI, a novel GPU accelerated logic gate simulator that enables ultra-fast power estimation for industry sized ASIC designs with millions of gates.
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules.
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
4-bit weights and 8-bit activations achieve near-full-precision accuracy for both BERT-base and BERT-large on SQuAD while reducing area by 26% compared to an 8-bit baseline.
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Moreover, the proposed CNN model is general and transferable to different designs.
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Experimental results on benchmark circuits show that our approach achieves 25% improvement in design quality or 37% reduction in sampling cost compared to random forest method, which is the kernel of a highly cited previous work.
