Search Results for author: Harris Teague

Found 6 papers, 2 papers with code

Rapid Switching and Multi-Adapter Fusion via Sparse High Rank Adapters

no code implementations22 Jul 2024 Kartikeya Bhardwaj, Nilesh Prasad Pandey, Sweta Priyadarshi, Viswanath Ganapathy, Rafael Esteves, Shreya Kadambi, Shubhankar Borse, Paul Whatmough, Risheek Garrepalli, Mart van Baalen, Harris Teague, Markus Nagel

In this paper, we propose Sparse High Rank Adapters (SHiRA) that directly finetune 1-2% of the base model weights while leaving others unchanged, thus, resulting in a highly sparse adapter.

Sparse High Rank Adapters

no code implementations19 Jun 2024 Kartikeya Bhardwaj, Nilesh Prasad Pandey, Sweta Priyadarshi, Viswanath Ganapathy, Rafael Esteves, Shreya Kadambi, Shubhankar Borse, Paul Whatmough, Risheek Garrepalli, Mart van Baalen, Harris Teague, Markus Nagel

However, from a mobile deployment standpoint, we can either avoid inference overhead in the fused mode but lose the ability to switch adapters rapidly, or suffer significant (up to 30% higher) inference latency while enabling rapid switching in the unfused mode.

Moccasin: Efficient Tensor Rematerialization for Neural Networks

1 code implementation27 Apr 2023 Burak Bartan, Haoming Li, Harris Teague, Christopher Lott, Bistra Dilkina

The deployment and training of neural networks on edge computing devices pose many challenges.

Edge-computing

Neural Topological Ordering for Computation Graphs

no code implementations13 Jul 2022 Mukul Gagrani, Corrado Rainone, Yang Yang, Harris Teague, Wonseok Jeon, Herke van Hoof, Weiliang Will Zeng, Piero Zappi, Christopher Lott, Roberto Bondesan

Recent works on machine learning for combinatorial optimization have shown that learning based approaches can outperform heuristic methods in terms of speed and performance.

2k BIG-bench Machine Learning +3

SwiftNet: Using Graph Propagation as Meta-knowledge to Search Highly Representative Neural Architectures

1 code implementation19 Jun 2019 Hsin-Pai Cheng, Tunhou Zhang, Yukun Yang, Feng Yan, Shi-Yu Li, Harris Teague, Hai Li, Yiran Chen

Designing neural architectures for edge devices is subject to constraints of accuracy, inference latency, and computational cost.

Neural Architecture Search

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