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Found 13 papers, 0 papers with code
microYOLO: Towards Single-Shot Object Detection on Microcontrollers
This work-in-progress paper presents results on the feasibility of single-shot object detection on microcontrollers using YOLO.
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers
On-device training of DNNs allows models to adapt and fine-tune to newly collected data or changing domains while deployed on microcontroller units (MCUs).
OpTC -- A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers
The AURIX 2xx and 3xx families of TriCore microcontrollers are widely used in the automotive industry and, recently, also in applications that involve machine learning tasks.
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations
Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs.
Combining Multi-Objective Bayesian Optimization with Reinforcement Learning for TinyML
Deploying deep neural networks (DNNs) on microcontrollers (TinyML) is a common trend to process the increasing amount of sensor data generated at the edge, but in practice, resource and latency constraints make it difficult to find optimal DNN candidates.
Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression
Large Deep Neural Networks (DNNs) are the backbone of today's artificial intelligence due to their ability to make accurate predictions when being trained on huge datasets.
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of SNNs, especially the very high degree of sparsity of neural output activations.
Multi-Objective Design Space Exploration for the Optimization of the HEVC Mode Decision Process
Finding the best possible encoding decisions for compressing a video sequence is a highly complex problem.
EXPLAINABLE AI-BASED DYNAMIC FILTER PRUNING OF CONVOLUTIONAL NEURAL NETWORKS
Our proposed architecture for dynamic pruning can be deployed on different hardware platforms.
HipaccVX: Wedding of OpenVX and DSL-based Code Generation
OpenVX promises to solve this issue for computer vision applications with a royalty-free industry standard that is based on a graph-execution model.
Efficient Computation of Probabilistic Dominance in Robust Multi-Objective Optimization
This paper introduces an empirical approach that enables an efficient comparison of candidate solutions with uncertain objectives that can follow arbitrary distributions.
Automatic Optimization of Hardware Accelerators for Image Processing
Therefore, in previous work, we have shown that elevating the description of image algorithms to an even higher abstraction level, by using a Domain-Specific Language (DSL), can significantly cut down the complexity for designing such algorithms for FPGAs.
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs
Multiresolution Analysis (MRA) is a mathematical method that is based on working on a problem at different scales.
