Search Results for author:
Found 22 papers, 9 papers with code
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Research has shown that convolutional neural networks contain significant redundancy, and high classification accuracy can be obtained even when weights and activations are reduced from floating point to binary values.
Scaling Binarized Neural Networks on Reconfigurable Logic
Binarized neural networks (BNNs) are gaining interest in the deep learning community due to their significantly lower computational and memory cost.
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks
A low precision deep neural network training technique for producing sparse, ternary neural networks is presented.
Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices
Neural networks have established as a generic and powerful means to approach challenging problems such as image classification, object detection or decision making.
SYQ: Learning Symmetric Quantization For Efficient Deep Neural Networks
An efficient way to reduce this complexity is to quantize the weight parameters and/or activations during training by approximating their distributions with a limited entry codebook.
FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs
In this paper, we present the first systematic exploration of this design space as a function of precision for Bidirectional Long Short-Term Memory (BiLSTM) neural network.
Optical Character Recognition
Optical Character Recognition (OCR)
+1
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
Given a neural network description, the tool optimizes for given platforms, design targets and a specific precision.
Hardware Architecture
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
DiracDeltaNet achieves competitive accuracy on ImageNet (88. 7\% top-5), but with 42$\times$ fewer parameters and 48$\times$ fewer OPs than VGG16.
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware
In order to address these implementation challenges, a broad spectrum of new customized and heterogeneous hardware architectures have emerged, often accompanied with co-designed algorithms to extract maximum benefit out of the hardware.
Hardware Architecture
Efficient Error-Tolerant Quantized Neural Network Accelerators
In particular, Convolutional Neural Networks (CNNs), are gaining popularity and are evaluated for deployment in safety critical applications such as self driving vehicles.
Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA
We hybridize genetic algorithms and simulated annealing with traditional bin packing heuristics to create flexible mappers capable of grouping parameter memories such that each group optimally fits FPGA on-chip memories.
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware.
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
Our experiments show that by injecting faults in the convolutional layers during training, highly accurate convolutional neural networks (CNNs) can be trained which exhibits much better error tolerance compared to the original.
Applications and Techniques for Fast Machine Learning in Science
In this community review report, we discuss applications and techniques for fast machine learning (ML) in science -- the concept of integrating power ML methods into the real-time experimental data processing loop to accelerate scientific discovery.
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators
We find that commonly-used low-power CNN inference accelerators based on spatial architectures are not optimized for both of these convolutional kernels.
QONNX: Representing Arbitrary-Precision Quantized Neural Networks
We present extensions to the Open Neural Network Exchange (ONNX) intermediate representation format to represent arbitrary-precision quantized neural networks.
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark
We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms.
Towards FPGA Implementation of Neural Network-Based Nonlinearity Mitigation Equalizers in Coherent Optical Transmission Systems
For the first time, recurrent and feedforward neural network-based equalizers for nonlinearity compensation are implemented in an FPGA, with a level of complexity comparable to that of a dispersion equalizer.
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performance.
Implementing Neural Network-Based Equalizers in a Coherent Optical Transmission System Using Field-Programmable Gate Arrays
The main results are divided into three parts: a performance comparison, an analysis of how activation functions are implemented, and a report on the complexity of the hardware.
Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs
However, the exploration of floating-point formats smaller than 8 bits and their comparison with integer quantization remains relatively limited.
ACCL+: an FPGA-Based Collective Engine for Distributed Applications
To facilitate the development of distributed applications with FPGAs, in this paper we propose ACCL+, an open-source versatile FPGA-based collective communication library.
