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Found 7 papers, 4 papers with code
ORIGAMI: A Heterogeneous Split Architecture for In-Memory Acceleration of Learning
To utilize available bandwidth without violating area and power budgets of logic layer, ORIGAMI comes with a computation-splitting compiler that divides an ML algorithm between in-memory accelerators and an out-of-the-memory platform in a balanced way and with minimum inter-communications.
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
To this end, we propose a new technique called Hermes, whose key idea is to: 1) accurately predict which load requests might go off-chip, and 2) speculatively fetch the data required by the predicted off-chip loads directly from the main memory, while also concurrently accessing the cache hierarchy for such loads.
TargetCall: Eliminating the Wasted Computation in Basecalling via Pre-Basecalling Filtering
However, for many applications, the majority of reads do no match the reference genome of interest (i. e., target reference) and thus are discarded in later steps in the genomics pipeline, wasting the basecalling computation.
TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems
In order to provide support for transcendental (and other hard-to-calculate) functions in general-purpose PIM systems, we present \emph{TransPimLib}, a library that provides CORDIC-based and LUT-based methods for trigonometric functions, hyperbolic functions, exponentiation, logarithm, square root, etc.
RawAlign: Accurate, Fast, and Scalable Raw Nanopore Signal Mapping via Combining Seeding and Alignment
mean) while improving accuracy by 1. 35$\times$ (1. 34$\times$) in terms of F-1 score on average (geo.
Accelerating Graph Neural Networks on Real Processing-In-Memory Systems
Graph Neural Network (GNN) execution involves both compute-intensive and memory-intensive kernels, the latter dominates the total time, being significantly bottlenecked by data movement between memory and processors.
Analysis of Distributed Optimization Algorithms on a Real Processing-In-Memory System
Processor-centric architectures (e. g., CPU, GPU) commonly used for modern ML training workloads are limited by the data movement bottleneck, i. e., due to repeatedly accessing the training dataset.
