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NeuroSteiner: A Graph Transformer for Wirelength Estimation
A core objective of physical design is to minimize wirelength (WL) when placing chip components on a canvas.
Bayesian Optimization for Macro Placement
Macro placement is the problem of placing memory blocks on a chip canvas.
Simulating Execution Time of Tensor Programs using Graph Neural Networks
Optimizing the execution time of tensor program, e. g., a convolution, involves finding its optimal configuration.
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