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Found 8 papers, 2 papers with code
Tailor: Altering Skip Connections for Resource-Efficient Inference
We argue that while a network's skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware efficient implementation with minimal to no accuracy loss.
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark
We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms.
Applications and Techniques for Fast Machine Learning in Science
In this community review report, we discuss applications and techniques for fast machine learning (ML) in science -- the concept of integrating power ML methods into the real-time experimental data processing loop to accelerate scientific discovery.
Hardware-efficient Residual Networks for FPGAs
Residual networks (ResNets) employ skip connections in their networks -- reusing activations from previous layers -- to improve training convergence, but these skip connections create challenges for hardware implementations of ResNets.
A Unified Model for Gate Level Propagation Analysis
To justify our model, we prove that Precise Hardware IFT is equivalent to gate level X-propagation and imprecise fault propagation.
Hardware Architecture
FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA
While WaveNet produces state-of-the art audio generation results, the naive inference implementation is quite slow; it takes a few minutes to generate just one second of audio on a high-end GPU.
Patient Specific Biomechanics Are Clinically Significant In Accurate Computer Aided Surgical Image Guidance
Augmented Reality is used in Image Guided surgery (AR IG) to fuse surgical landmarks from preoperative images into a video overlay.
Parallel Programming for FPGAs
This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-specific FPGA systems.
Hardware Architecture
