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Found 9 papers, 1 papers with code
DOCTOR: Dynamic On-Chip Temporal Variation Remediation Toward Self-Corrected Photonic Tensor Accelerators
While off-chip noise-aware training and on-chip training have been proposed to enhance the variation tolerance of optical neural accelerators with moderate, static noise, we observe a notable performance degradation over time due to temporally drifting variations, which requires a real-time, in-situ calibration mechanism.
ChipNeMo: Domain-Adapted LLMs for Chip Design
ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design.
Analysis of Optical Loss and Crosstalk Noise in MZI-based Coherent Photonic Neural Networks
The proposed models can be applied to any SP-NN architecture with different configurations to analyze the effect of loss and crosstalk.
Characterizing Coherent Integrated Photonic Neural Networks under Imperfections
Integrated photonic neural networks (IPNNs) are emerging as promising successors to conventional electronic AI accelerators as they offer substantial improvements in computing speed and energy efficiency.
Characterization and Optimization of Integrated Silicon-Photonic Neural Networks under Fabrication-Process Variations
Simulation results for two example SPNNs of different scales under realistic and correlated FPVs indicate that the optimized MZIs can improve the inferencing accuracy by up to 93. 95% for the MNIST handwritten digit dataset -- considered as an example in this paper -- which corresponds to a <0. 5% accuracy loss compared to the variation-free case.
LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks
Compared to electronic accelerators, integrated silicon-photonic neural networks (SP-NNs) promise higher speed and energy efficiency for emerging artificial-intelligence applications.
Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis
Singular-value-decomposition-based coherent integrated photonic neural networks (SC-IPNNs) have a large footprint, suffer from high static power consumption for training and inference, and cannot be pruned using conventional DNN pruning techniques.
CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks
We propose a novel hardware-aware magnitude pruning technique for coherent photonic neural networks.
Modeling Silicon-Photonic Neural Networks under Uncertainties
Silicon-photonic neural networks (SPNNs) offer substantial improvements in computing speed and energy efficiency compared to their digital electronic counterparts.
