no code implementations • 9 Jan 2025 • Ravi G. Patel, T. Patrick Xiao, Sapan Agarwal, Christopher Bennett
Recent work has demonstrated that Bayesian neural networks (BNN's) trained with mean field variational inference (MFVI) can be implemented in analog hardware, promising orders of magnitude energy savings compared to the standard digital implementations.
no code implementations • 18 Oct 2022 • Ethan Ancell, Christopher Bennett, Bert Debusschere, Sapan Agarwal, Park Hays, T. Patrick Xiao
Bayesian neural networks (BNNs) are an important type of neural network with built-in capability for quantifying uncertainty.
Generative Adversarial Network
Out of Distribution (OOD) Detection
+1
no code implementations • 3 Sep 2021 • T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar, Prashant Saxena, Vineet Agrawal, Sapan Agarwal, Matthew J. Marinella
Specialized accelerators have recently garnered attention as a method to reduce the power consumption of neural network inference.
no code implementations • 2 Apr 2020 • Christopher H. Bennett, T. Patrick Xiao, Ryan Dellana, Vineet Agrawal, Ben Feinberg, Venkatraman Prabhakar, Krishnaswamy Ramkumar, Long Hinh, Swatilekha Saha, Vijay Raghavan, Ramesh Chettuvetty, Sapan Agarwal, Matthew J. Marinella
Non-volatile memory arrays can deploy pre-trained neural network models for edge inference.
no code implementations • 25 Feb 2020 • Christopher H. Bennett, Ryan Dellana, T. Patrick Xiao, Ben Feinberg, Sapan Agarwal, Suma Cardwell, Matthew J. Marinella, William Severa, Brad Aimone
Neuromorphic-style inference only works well if limited hardware resources are maximized properly, e. g. accuracy continues to scale with parameters and complexity in the face of potential disturbance.
1 code implementation • 27 Oct 2017 • Sapan Agarwal, Corey M. Hudson
This work presents a new classifier that is specifically designed to be fully interpretable.
no code implementations • 31 Jul 2017 • Matthew J. Marinella, Sapan Agarwal, Alexander Hsia, Isaac Richter, Robin Jacobs-Gedrim, John Niroula, Steven J. Plimpton, Engin Ipek, Conrad D. James
A detailed circuit and device-level analysis of energy, latency, area, and accuracy are given and compared to relevant designs using standard digital ReRAM and SRAM operations.