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Found 8 papers, 3 papers with code
Timing-Driven Global Placement by Efficient Critical Path Extraction
Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue.
E2ESlack: An End-to-End Graph-Based Framework for Pre-Routing Slack Prediction
The framework includes a TimingParser that supports DEF, SDF and LIB files for feature extraction and graph construction, an arrival time prediction model and a fast RAT estimation module.
Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer
In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics.
Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
We executed six state-of-the-art AI-based chip placement algorithms on these designs and plugged the results of each single-point algorithm into the physical implementation workflow to obtain the final PPA results.
Escaping Local Optima in Global Placement
Placement is crucial in the physical design, as it greatly affects power, performance, and area metrics.
PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling
First, we propose global circuit training to pre-train a graph auto-encoder that learns the global graph embedding from circuit netlist.
LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
Since circuit can be represented with HDL in a textual format, it is reasonable to question whether LLMs can be leveraged in the EDA field to achieve fully automated chip design and generate circuits with improved power, performance, and area (PPA).
RITA: Boost Driving Simulators with Realistic Interactive Traffic Flow
High-quality traffic flow generation is the core module in building simulators for autonomous driving.
