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Found 2 papers, 1 papers with code
Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression
Deep learning algorithms have shown tremendous success in many recognition tasks; however, these algorithms typically include a deep neural network (DNN) structure and a large number of parameters, which makes it challenging to implement them on power/area-constrained embedded platforms.
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations
We present a new back propagation based training algorithm for discrete-time spiking neural networks (SNN).
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