Search Results for author:
Found 35 papers, 7 papers with code
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
%Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks.
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking.
Can deepfakes be created by novice users?
We conclude that creating Deepfakes is a simple enough task for a novice user given adequate tools and time; however, the resulting Deepfakes are not sufficiently real-looking and are unable to completely fool detection software as well as human examiners
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Oracle-less machine learning (ML) attacks have broken various logic locking schemes.
Precoding-oriented Massive MIMO CSI Feedback Design
Downlink massive multiple-input multiple-output (MIMO) precoding algorithms in frequency division duplexing (FDD) systems rely on accurate channel state information (CSI) feedback from users.
A Minimax Approach Against Multi-Armed Adversarial Attacks Detection
Multi-armed adversarial attacks, in which multiple algorithms and objective loss functions are simultaneously used at evaluation time, have been shown to be highly successful in fooling state-of-the-art adversarial examples detectors while requiring no specific side information about the detection mechanism.
Hyper-parameter Tuning for Fair Classification without Sensitive Attribute Access
Recent work has sought to train fair models without sensitive attributes on training data.
An Upper Bound for the Distribution Overlap Index and Its Applications
In domain shift analysis, we propose a theorem based on our bound.
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors.
Privacy-Preserving Collaborative Learning through Feature Extraction
As a baseline, in Cooperatively Trained Feature Extractor (CTFE) Learning, the entities train models by sharing raw data.
Fairness via In-Processing in the Over-parameterized Regime: A Cautionary Tale
We further show that MinDiff optimization is very sensitive to choice of batch size in the under-parameterized regime.
MALICE: Manipulation Attacks on Learned Image ComprEssion
To characterize the robustness of state-of-the-art learned image compression, we mount white-box and black-box attacks.
Feature Compression for Rate Constrained Object Detection on the Edge
In this work, we consider a "split computation" system to offload a part of the computation of the YOLO object detection model.
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Generating sub-optimal synthesis transformation sequences ("synthesis recipe") is an important problem in logic synthesis.
Selective Network Linearization for Efficient Private Inference
To reduce PI latency we propose a gradient-based algorithm that selectively linearizes ReLUs while maintaining prediction accuracy.
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design.
Sphynx: ReLU-Efficient Network Design for Private Inference
The emergence of deep learning has been accompanied by privacy concerns surrounding users' data and service providers' models.
Circa: Stochastic ReLUs for Private Deep Learning
In this paper we re-think the ReLU computation and propose optimizations for PI tailored to properties of neural networks.
Generating and Characterizing Scenarios for Safety Testing of Autonomous Vehicles
Extracting interesting scenarios from real-world data as well as generating failure cases is important for the development and testing of autonomous systems.
DeepReDuce: ReLU Reduction for Fast Private Inference
This paper proposes DeepReDuce: a set of optimizations for the judicious removal of ReLUs to reduce private inference latency.
Bait and Switch: Online Training Data Poisoning of Autonomous Driving Systems
We show that by controlling parts of a physical environment in which a pre-trained deep neural network (DNN) is being fine-tuned online, an adversary can launch subtle data poisoning attacks that degrade the performance of the system.
Detecting Backdoors in Neural Networks Using Novel Feature-Based Anomaly Detection
This paper proposes a new defense against neural network backdooring attacks that are maliciously trained to mispredict in the presence of attacker-chosen triggers.
On Evaluating Neural Network Backdoor Defenses
Deep neural networks (DNNs) demonstrate superior performance in various fields, including scrutiny and security.
Subverting Privacy-Preserving GANs: Hiding Secrets in Sanitized Images
Unprecedented data collection and sharing have exacerbated privacy concerns and led to increasing interest in privacy-preserving tools that remove sensitive attributes from images while maintaining useful information for other tasks.
Adversarially Robust Learning via Entropic Regularization
In this paper we propose a new family of algorithms, ATENT, for training adversarially robust deep neural networks.
CryptoNAS: Private Inference on a ReLU Budget
Machine learning as a service has given raise to privacy concerns surrounding clients' data and providers' models and has catalyzed research in private inference (PI): methods to process inferences without disclosing inputs.
Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks
Deep learning (DL) offers potential improvements throughout the CAD tool-flow, one promising application being lithographic hotspot detection.
NNoculation: Catching BadNets in the Wild
This paper proposes a novel two-stage defense (NNoculation) against backdoored neural networks (BadNets) that, repairs a BadNet both pre-deployment and online in response to backdoored test inputs encountered in the field.
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection
There is substantial interest in the use of machine learning (ML) based techniques throughout the electronic computer-aided design (CAD) flow, particularly those based on deep learning.
FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
FATE proposes two novel ideas: (i) DelayNet, a DNN based timing model for MAC units; and (ii) a statistical sampling methodology that reduces the number of MAC operations for which timing simulations are performed.
Fine-Pruning: Defending Against Backdooring Attacks on Deep Neural Networks
Our work provides the first step toward defenses against backdoor attacks in deep neural networks.
Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
Due to their growing popularity and computational cost, deep neural networks (DNNs) are being targeted for hardware acceleration.
ThUnderVolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Neural Network Accelerators
Hardware accelerators are being increasingly deployed to boost the performance and energy efficiency of deep neural network (DNN) inference.
BadNets: Identifying Vulnerabilities in the Machine Learning Model Supply Chain
These results demonstrate that backdoors in neural networks are both powerful and---because the behavior of neural networks is difficult to explicate---stealthy.
SafetyNets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud
Specifically, SafetyNets develops and implements a specialized interactive proof (IP) protocol for verifiable execution of a class of deep neural networks, i. e., those that can be represented as arithmetic circuits.
