Search Results for author: Siyuan Xu

Found 11 papers, 4 papers with code

TransPlace: Transferable Circuit Global Placement via Graph Neural Network

1 code implementation10 Jan 2025 Yunbo Hou, Haoran Ye, Yingxue Zhang, Siyuan Xu, Guojie Song

Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance.

Graph Neural Network

Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer

1 code implementation10 Dec 2024 Ke Xue, Ruo-Tong Chen, Xi Lin, Yunqi Shi, Shixiong Kai, Siyuan Xu, Chao Qian

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics.

reinforcement-learning Reinforcement Learning +1

Meta-Reinforcement Learning with Universal Policy Adaptation: Provable Near-Optimality under All-task Optimum Comparator

no code implementations13 Oct 2024 Siyuan Xu, Minghui Zhu

Meta-reinforcement learning (Meta-RL) has attracted attention due to its capability to enhance reinforcement learning (RL) algorithms, in terms of data efficiency and generalizability.

Bilevel Optimization Meta Reinforcement Learning +3

Distance-Forward Learning: Enhancing the Forward-Forward Algorithm Towards High-Performance On-Chip Learning

no code implementations27 Aug 2024 Yujie Wu, Siyuan Xu, Jibin Wu, Lei Deng, Mingkun Xu, Qinghao Wen, Guoqi Li

The Forward-Forward (FF) algorithm was recently proposed as a local learning method to address the limitations of backpropagation (BP), offering biological plausibility along with memory-efficient and highly parallelized computational benefits.

Metric Learning

Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms

no code implementations3 Jul 2024 Zhihai Wang, Zijie Geng, Zhaojie Tu, Jie Wang, Yuxi Qian, Zhexuan Xu, Ziyan Liu, Siyuan Xu, Zhentao Tang, Shixiong Kai, Mingxuan Yuan, Jianye Hao, Bin Li, Yongdong Zhang, Feng Wu

We executed six state-of-the-art AI-based chip placement algorithms on these designs and plugged the results of each single-point algorithm into the physical implementation workflow to obtain the final PPA results.

Benchmarking

RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network

1 code implementation4 Jun 2024 Yunbo Hou, Haoran Ye, Yingxue Zhang, Siyuan Xu, Guojie Song

Placement is a critical and challenging step of modern chip design, with routability being an essential indicator of placement quality.

Graph Neural Network

Federated reinforcement learning for robot motion planning with zero-shot generalization

no code implementations20 Mar 2024 Zhenyuan Yuan, Siyuan Xu, Minghui Zhu

This paper considers the problem of learning a control policy for robot motion planning with zero-shot generalization, i. e., no data collection and policy adaptation is needed when the learned policy is deployed in new environments.

Motion Planning Zero-shot Generalization

Escaping Local Optima in Global Placement

no code implementations28 Feb 2024 Ke Xue, Xi Lin, Yunqi Shi, Shixiong Kai, Siyuan Xu, Chao Qian

Placement is crucial in the physical design, as it greatly affects power, performance, and area metrics.

LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation

1 code implementation28 Dec 2023 RuiZhe Zhong, Xingbo Du, Shixiong Kai, Zhentao Tang, Siyuan Xu, Hui-Ling Zhen, Jianye Hao, Qiang Xu, Mingxuan Yuan, Junchi Yan

Since circuit can be represented with HDL in a textual format, it is reasonable to question whether LLMs can be leveraged in the EDA field to achieve fully automated chip design and generate circuits with improved power, performance, and area (PPA).

Answer Generation Chatbot +1

Efficient Gradient Approximation Method for Constrained Bilevel Optimization

no code implementations3 Feb 2023 Siyuan Xu, Minghui Zhu

Bilevel optimization has been developed for many machine learning tasks with large-scale and high-dimensional data.

Bilevel Optimization Hyperparameter Optimization +1

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