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Found 5 papers, 0 papers with code
Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting
Formal Property Verification (FPV), using SystemVerilog Assertions (SVA), is crucial for ensuring the completeness of design with respect to the specification.
ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters
Despite the inclusion of floating-point parameters in BNN architectures to improve accuracy, our findings reveal that BNNs are highly sensitive to deviations in these parameters caused by memory faults.
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization
The imperative to deploy Deep Neural Network (DNN) models on resource-constrained edge devices, spurred by privacy concerns, has become increasingly apparent.
T-RECX: Tiny-Resource Efficient Convolutional neural networks with early-eXit
In this paper, we show how such models can be enhanced by the addition of an early exit intermediate classifier.
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Recent breakthroughs in ML have produced new classes of models that allow ML inference to run directly on milliwatt-powered IoT devices.
