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Found 12 papers, 1 papers with code
Towards Exact Gradient-based Training on Analog In-memory Computing
Given the high economic and environmental costs of using large vision or language models, analog in-memory accelerators present a promising solution for energy-efficient AI.
Fast offset corrected in-memory training
In-memory computing with resistive crossbar arrays has been suggested to accelerate deep-learning workloads in highly efficient manner.
Neural Network Training with Asymmetric Crosspoint Elements
Analog crossbar arrays comprising programmable nonvolatile resistors are under intense investigation for acceleration of deep neural network training.
A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays
We introduce the IBM Analog Hardware Acceleration Kit, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PyTorch (freely available at https://github. com/IBM/aihwkit).
Algorithm for Training Neural Networks on Resistive Device Arrays
Hardware architectures composed of resistive cross-point device arrays can provide significant power and speed benefits for deep neural network training workloads using stochastic gradient descent (SGD) and backpropagation (BP) algorithm.
Zero-shifting Technique for Deep Neural Network Training on Resistive Cross-point Arrays
By using this zero-shifting method, we show that network performance dramatically improves for imbalanced synapse devices.
Training large-scale ANNs on simulated resistive crossbar arrays
Accelerating training of artificial neural networks (ANN) with analog resistive crossbar arrays is a promising idea.
Efficient ConvNets for Analog Arrays
Analog arrays are a promising upcoming hardware technology with the potential to drastically speed up deep learning.
Training LSTM Networks with Resistive Cross-Point Devices
In our previous work we have shown that resistive cross point devices, so called Resistive Processing Unit (RPU) devices, can provide significant power and speed benefits when training deep fully connected networks as well as convolutional neural networks.
Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training
Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU.
Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices
This concept of Resistive Processing Unit (RPU) devices we extend here towards convolutional neural networks (CNNs).
Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices
In recent years, deep neural networks (DNN) have demonstrated significant business impact in large scale analysis and classification tasks such as speech recognition, visual object detection, pattern extraction, etc.
