no code implementations • 13 May 2025 • Sebastian Billaudelle, Laura Kriener, Filippo Moro, Tristan Torchet, Melika Payvand
We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model.
no code implementations • 8 Aug 2023 • Zhe Su, Hyunjung Hwang, Tristan Torchet, Giacomo Indiveri
In particular the core interface that manages inter-core spike communication is a crucial component as it represents the bottleneck of Power-Performance-Area (PPA) especially for the arbitration architecture and the routing memory.