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MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units
We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model.
Core interface optimization for multi-core neuromorphic processors
In particular the core interface that manages inter-core spike communication is a crucial component as it represents the bottleneck of Power-Performance-Area (PPA) especially for the arbitration architecture and the routing memory.
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