Search Results for author: Viduneth Ariyarathna

Found 3 papers, 0 papers with code

Towards a Low-SWaP 1024-beam Digital Array: A 32-beam Sub-system at 5.8 GHz

no code implementations19 Jul 2022 Arjuna Madanayake, Viduneth Ariyarathna, Suresh Madishetty, Sravan Pulipati, R. J. Cintra, Diego Coelho, Raíza Oliveira, Fábio M. Bayer, Leonid Belostotski, Soumyajit Mandal, Theodore S. Rappaport

Arithmetic complexity due to multiplication is reduced from the FFT complexity of $\mathcal{O}(N\: \log N)$ for DFT realizations, down to zero, thus yielding a 46% and 55% reduction in chip area and dynamic power consumption, respectively, for the $N=32$ case considered.

Xilinx RF-SoC-based Digital Multi-Beam Array Processors for 28/60~GHz Wireless Testbeds

no code implementations3 Aug 2020 Sravan Pulipati, Viduneth Ariyarathna, Aditya Dhananjay, Mohammed E. Eltayeb, Marco Mezzavilla, Josep M. Jornet, Soumyajit Mandal, Shubhendu Bhardwaj, Arjuna Madanayake

Emerging wireless applications such as 5G cellular, large intelligent surfaces (LIS), and holographic massive MIMO require antenna array processing at mm-wave frequencies with large numbers of independent digital transceivers.

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