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Found 2 papers, 2 papers with code
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large language models, garnering significant attention.
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Our 13B model (ChipGPT-FT) has a pass rate improvement compared with GPT-3. 5 in Verilog generation and outperforms in EDA script (i. e., SiliconCompiler) generation with only 200 EDA script data.
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