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Found 7 papers, 2 papers with code
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation
In this study, we propose HiKonv, a unified solution that maximizes the throughput of convolution on a given underlying processing unit with low-bitwidth quantized data inputs through novel bit-wise management and parallel computation.
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Quantization for Convolutional Neural Network (CNN) has shown significant progress with the intention of reducing the cost of computation and storage with low-bitwidth data inputs.
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
We implement our proposed accelerator on multiple FPGAs, which outperforms the state-of-the-art designs in terms of both throughput and DSP efficiency.
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
We design an efficient FPGA-based accelerator for our novel BNN model that supports the fractional activations.
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
We formulate the co-search problem by fusing DNN search variables and hardware implementation variables into one solution space, and maximize both algorithm accuracy and hardware implementation quality.
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
The rapidly growing demands for powerful AI algorithms in many application domains have motivated massive investment in both high-quality deep neural network (DNN) models and high-efficiency implementations.
Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAs
Deep Convolutional Neural Networks have become a Swiss knife in solving critical artificial intelligence tasks.
