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Found 12 papers, 9 papers with code
A2Q+: Improving Accumulator-Aware Weight Quantization
Recent studies show that also reducing the precision of the accumulator can further improve hardware efficiency at the risk of numerical overflow, which introduces arithmetic errors that can degrade model accuracy.
Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark
We present our development experience and recent results for the MLPerf Tiny Inference Benchmark on field-programmable gate array (FPGA) platforms.
QONNX: Representing Arbitrary-Precision Quantized Neural Networks
We present extensions to the Open Neural Network Exchange (ONNX) intermediate representation format to represent arbitrary-precision quantized neural networks.
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators
We find that commonly-used low-power CNN inference accelerators based on spatial architectures are not optimized for both of these convolutional kernels.
Ps and Qs: Quantization-aware pruning for efficient low latency neural network inference
We study various configurations of pruning during quantization-aware training, which we term quantization-aware pruning, and the effect of techniques like regularization, batch normalization, and different pruning schemes on performance, computational complexity, and information content metrics.
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware.
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing
BISMO, a vectorized bit-serial matrix multiplication overlay for reconfigurable computing, previously utilized the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism.
Hardware Architecture
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
Given a neural network description, the tool optimizes for given platforms, design targets and a specific precision.
Hardware Architecture
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
BISMO utilizes the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism.
Hardware Architecture
Streamlined Deployment for Quantized Neural Networks
Quantized Neural Networks (QNNs) have emerged as a potential solution to this problem, promising to offer most of the DNN accuracy benefits with much lower computational cost.
Scaling Binarized Neural Networks on Reconfigurable Logic
Binarized neural networks (BNNs) are gaining interest in the deep learning community due to their significantly lower computational and memory cost.
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Research has shown that convolutional neural networks contain significant redundancy, and high classification accuracy can be obtained even when weights and activations are reduced from floating point to binary values.
