no code implementations • 1 May 2025 • Chaitali Bhattacharyya, Yeseong Kim
Furthermore, applying these datasets to fine-tune pretrained LLMs without pruning also improves their domain-specific accuracy, highlighting the robustness of our approach.
no code implementations • 21 Nov 2024 • Sungheon Jeong, Hamza Errahmouni Barkam, Sanggeon Yun, Yeseong Kim, Shaahin Angizi, Mohsen Imani
Hyperdimensional computing (HDC) enables efficient data encoding and processing in high-dimensional space, benefiting machine learning and data analysis.
no code implementations • 14 May 2022 • Yang Ni, Danny Abraham, Mariam Issa, Yeseong Kim, Pietro Mercati, Mohsen Imani
Our evaluation shows QHD capability for real-time learning, providing 34. 6 times speedup and significantly better quality of learning than DQN.
no code implementations • Conference 2022 • Jun S. Shim, Bogyeong Han, Yeseong Kim, Jihong Kim
Many system-level management and optimization techniques need accurate estimates of power consumption and performance.
no code implementations • 17 Feb 2022 • Jisung Park, Jeoggyun Kim, Yeseong Kim, Sungjin Lee, Onur Mutlu
Data reduction in storage systems is becoming increasingly important as an effective solution to minimize the management cost of a data center.
no code implementations • 1 Oct 2021 • Zhuowen Zou, Haleh Alimohamadi, Farhad Imani, Yeseong Kim, Mohsen Imani
Particularly, Spiking Neural Networks (SNNs) and HyperDimensional Computing (HDC) have shown promising results in enabling efficient and robust cognitive learning.
no code implementations • 20 Jul 2020 • Behnam Khaleghi, Sahand Salamat, Anthony Thomas, Fatemeh Asgarinejad, Yeseong Kim, Tajana Rosing
In this paper, we propose SHEARer, an algorithm-hardware co-optimization to improve the performance and energy consumption of HD computing.
no code implementations • 15 Jun 2018 • Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
To enable in-memory processing, RAPIDNN reinterprets a DNN model and maps it into a specialized accelerator, which is designed using non-volatile memory blocks that model four fundamental DNN operations, i. e., multiplication, addition, activation functions, and pooling.