High-Level Synthesis
32 papers with code • 0 benchmarks • 0 datasets
Benchmarks
These leaderboards are used to track progress in High-Level Synthesis
Most implemented papers
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Recent work has shown that Field-Programmable Gate Arrays (FPGAs) play an important role in the acceleration of Machine Learning applications.
Fast inference of deep neural networks in FPGAs for particle physics
hls-fpga-machine-learning/hls4ml
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For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns.
Hardware-Efficient Deconvolution-Based GAN for Edge Computing
Azzam-Alhussain/QDCGAN-PYNQ
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Generative Adversarial Networks (GAN) are cutting-edge algorithms for generating new data samples based on the learned data distribution.
Allo: A Programming Model for Composable Accelerator Design
For the GPT2 model, the inference latency of the Allo generated accelerator is 1. 7x faster than the NVIDIA A100 GPU with 5. 4x higher energy efficiency, demonstrating the capability of Allo to handle large-scale designs.
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
DiracDeltaNet achieves competitive accuracy on ImageNet (88. 7\% top-5), but with 42$\times$ fewer parameters and 48$\times$ fewer OPs than VGG16.
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning
We implement a framework in the context of the LLVM compiler to optimize the ordering for HLS programs and compare the performance of deep reinforcement learning to state-of-the-art algorithms that address the phase-ordering problem.
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
We compare the performance of AutoPhase to state-of-the-art algorithms that address the phase-ordering problem.
A scalable and efficient convolutional neural network accelerator using HLS for a System on Chip design
This paper presents a configurable Convolutional Neural Network Accelerator (CNNA) for a System on Chip design (SoC).
ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network
johngear/eecs504
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Convolutional Neural Networks (CNNs) presently achieve record-breaking accuracies in all image understanding benchmarks, but have a very high computational complexity.
Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs
We develop and study FPGA implementations of algorithms for charged particle tracking based on graph neural networks.
