Design Synthesis
7 papers with code • 0 benchmarks • 0 datasets
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Most implemented papers
PaDGAN: A Generative Adversarial Network for Performance Augmented Diverse Designs
wchen459/PaDGAN
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With this new loss function, we develop a variant of the Generative Adversarial Network, named "Performance Augmented Diverse Generative Adversarial Network" or PaDGAN, which can generate novel high-quality designs with good coverage of the design space.
CreativeGAN: Editing Generative Adversarial Networks for Creative Design Synthesis
GAN models, however, are not capable of generating unique designs, a key to innovation and a major gap in AI-based design automation applications.
Range-GAN: Range-Constrained Generative Adversarial Network for Conditioned Design Synthesis
This work laid the foundation for data-driven inverse design problems where we consider range constraints and there are sparse regions in the condition space.
BIKED: A Dataset for Computational Bicycle Design with Machine Learning Benchmarks
In this paper, we present "BIKED," a dataset comprised of 4500 individually designed bicycle models sourced from hundreds of designers.
PcDGAN: A Continuous Conditional Diverse Generative Adversarial Network For Inverse Design
pcdgan/PcDGAN
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Engineering design tasks often require synthesizing new designs that meet desired performance requirements.
Conditional Cross-Design Synthesis Estimators for Generalizability in Medicaid
To generalize to a target population represented by a union of these data, we propose a class of novel conditional cross-design synthesis estimators that combine randomized and observational data, while addressing their respective biases.
Diffusion Models Beat GANs on Topology Optimization
By introducing diffusion models to topology optimization, we show that conditional diffusion models have the ability to outperform GANs in engineering design synthesis applications too.
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
HLSFactory has three main stages: 1) a design space expansion stage to elaborate single HLS designs into large design spaces using various optimization directives across multiple vendor tools, 2) a design synthesis stage to execute HLS and FPGA tool flows concurrently across designs, and 3) a data aggregation stage for extracting standardized data into packaged datasets for ML usage.
