Search Results for author:
Found 2 papers, 0 papers with code
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect
Our mapping strategy and system setup is scaled starting from the single core level up to 128 cores, thereby showing the limits of the selected approach.
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration
In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e. g. in the well-known ImageNet challenge.
Cannot find the paper you are looking for? You can
Submit a new open access paper.
