no code implementations • 25 Nov 2020 • Eitaro Hamada, Yuki Fujii, Youichi Igarashi, Masahiro Ikeno, Satoshi Mihara, Hajime Nishiguchi, Kou Oishi, Tomohisa Uchida, Kazuki Ueno, Hiroshi Yamaguchi
In order to decrease the number of vacuum feedthroughs drastically, we developed a network processor with a daisy-chain function of Gigabit Ethernet for the FPGA on the ROESTI.
Instrumentation and Detectors