Learning-driven Physically-aware Large-scale Circuit Gate Sizing

no code implementations • 13 Mar 2024 • Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi

Gate sizing plays an important role in timing optimization after physical design.

A Crosstalk-Aware Timing Prediction Method in Routing

no code implementations • 7 Mar 2024 • Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Longxing Shi

With shrinking interconnect spacing in advanced technology nodes, existing timing predictions become less precise due to the challenging quantification of crosstalk-induced delay.