FPGA Implementations of 3D-SIMD Processor Architecture for Deep Neural Networks Using Relative Indexed Compressed Sparse Filter Encoding Format and Stacked Filters Stationary Flow

28 Mar 2018 Yuechao Gao Nianhong Liu Sheng Zhang

It is a challenging task to deploy computationally and memory intensive State-of-the-art deep neural networks (DNNs) on embedded systems with limited hardware resources and power budgets. Recently developed techniques like Deep Compression make it possible to fit large DNNs, such as AlexNet and VGGNet, fully in on-chip SRAM... (read more)

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Methods used in the Paper


METHOD TYPE
1x1 Convolution
Convolutions
Convolution
Convolutions
Local Response Normalization
Normalization
Grouped Convolution
Convolutions
ReLU
Activation Functions
Dropout
Regularization
Dense Connections
Feedforward Networks
Max Pooling
Pooling Operations
Softmax
Output Functions
AlexNet
Convolutional Neural Networks