VTR: An Optimized Vision Transformer for SAR ATR Acceleration on FPGA

no code implementations • 6 Apr 2024 • Sachini Wickramasinghe, Dhruv Parikh, Bingyi Zhang, Rajgopal Kannan, Viktor Prasanna, Carl Busart

We directly train this model on SAR datasets which have limited training samples to evaluate its effectiveness for SAR ATR applications.

Accelerating ViT Inference on FPGA through Static and Dynamic Pruning

no code implementations • 21 Mar 2024 • Dhruv Parikh, Shouyi Li, Bingyi Zhang, Rajgopal Kannan, Carl Busart, Viktor Prasanna

For algorithm design, we systematically combine a hardware-aware structured block-pruning method for pruning model parameters and a dynamic token pruning method for removing unimportant token vectors.