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Found 34 papers, 14 papers with code
GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA
Moreover, GCV-Turbo supports the execution of the standalone CNNs or GNNs, achieving performance comparable to that of state-of-the-art CNN (GNN) accelerators for widely used CNN-only (GNN-only) models.
TabConv: Low-Computation CNN Inference via Table Lookups
TabConv preserves over 93% of the original model's performance while reducing arithmetic operations by 36. 5%, 25. 8%, and 99. 4% for ResNet-18 on CIFAR-10, CIFAR-100, and MNIST, respectively, 35. 6% and 99. 3% for ResNet-34 on CIFAR-10 and MNIST, and 98. 9% for NIN on MNIST, achieving low-computation inference.
VTR: An Optimized Vision Transformer for SAR ATR Acceleration on FPGA
We directly train this model on SAR datasets which have limited training samples to evaluate its effectiveness for SAR ATR applications.
FACTUAL: A Novel Framework for Contrastive Learning Based Robust SAR Image Classification
FACTUAL consists of two components: (1) Differing from existing works, a novel perturbation scheme that incorporates realistic physical adversarial attacks (such as OTSA) to build a supervised adversarial pre-training network.
Uncertainty-Aware SAR ATR: Defending Against Adversarial Attacks via Bayesian Neural Networks
Adversarial attacks have demonstrated the vulnerability of Machine Learning (ML) image classifiers in Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR) systems.
Accelerating ViT Inference on FPGA through Static and Dynamic Pruning
For algorithm design, we systematically combine a hardware-aware structured block-pruning method for pruning model parameters and a dynamic token pruning method for removing unimportant token vectors.
PaCKD: Pattern-Clustered Knowledge Distillation for Compressing Memory Access Prediction Models
Deep neural networks (DNNs) have proven to be effective models for accurate Memory Access Prediction (MAP), a critical task in mitigating memory latency through data prefetching.
ME-ViT: A Single-Load Memory-Efficient FPGA Accelerator for Vision Transformers
We evaluate ME-ViT on systolic array sizes of 32 and 16, achieving up to a 9. 22$\times$ and 17. 89$\times$ overall improvement in memory bandwidth, and a 2. 16$\times$ improvement in throughput per DSP for both designs over state-of-the-art ViT accelerators on FPGA.
TASER: Temporal Adaptive Sampling for Fast and Accurate Dynamic Graph Representation Learning
Recently, Temporal Graph Neural Networks (TGNNs) have demonstrated state-of-the-art performance in various high-impact applications, including fraud detection and content recommendation.
A Single Graph Convolution Is All You Need: Efficient Grayscale Image Classification
Our experimental results on benchmark grayscale image datasets demonstrate the effectiveness of the proposed model, achieving vastly lower latency (up to 16$\times$ less) and competitive or leading performance compared to other state-of-the-art image classification models on various domain-specific grayscale image classification datasets.
Ranked #16 on
Image Classification
on Fashion-MNIST
PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images
This detailed information includes the SAR image features that contributed to the classification, the classification confidence, and the probability of the identified object being classified as a different object type or class.
Benchmarking Deep Learning Classifiers for SAR Automatic Target Recognition
Synthetic Aperture Radar SAR Automatic Target Recognition ATR is a key technique of remote-sensing image recognition which can be supported by deep neural networks The existing works of SAR ATR mostly focus on improving the accuracy of the target recognition while ignoring the systems performance in terms of speed and storage which is critical to real-world applications of SAR ATR For decision-makers aiming to identify a proper deep learning model to deploy in a SAR ATR system it is important to understand the performance of different candidate deep learning models and determine the best model accordingly This paper comprehensively benchmarks several advanced deep learning models for SAR ATR with multiple distinct SAR imagery datasets Specifically we train and test five SAR image classifiers based on Residual Neural Networks ResNet18 ResNet34 ResNet50 Graph Neural Network GNN and Vision Transformer for Small-Sized Datasets (SS-ViT) We select three datasets MSTAR GBSAR and SynthWakeSAR that offer heterogeneity We evaluate and compare the five classifiers concerning their classification accuracy runtime performance in terms of inference throughput and analytical performance in terms of number of parameters number of layers model size and number of operations Experimental results show that the GNN classifier outperforms with respect to throughput and latency However it is also shown that no clear model winner emerges from all of our chosen metrics and a one model rules all case is doubtful in the domain of SAR ATR
Realistic Scatterer Based Adversarial Attacks on SAR Image Classifiers
Instead, adversarial attacks should be able to be implemented by physical actions, for example, placing additional false objects as scatterers around the on-ground target to perturb the SAR image and fool the SAR ATR.
Characterizing Speed Performance of Multi-Agent Reinforcement Learning
Multi-Agent Reinforcement Learning (MARL) has achieved significant success in large-scale AI systems and big-data applications such as smart grids, surveillance, etc.
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
To exploit data sparsity during inference, we devise a runtime kernel mapping strategy that dynamically assigns computation tasks to the PL and AIE based on data sparsity.
DistTGL: Distributed Memory-Based Temporal Graph Neural Network Training
Evenworse, the tremendous overhead to synchronize the node memory make it impractical to be deployed to distributed GPU clusters.
Graph Neural Network for Accurate and Low-complexity SAR ATR
In this work, we propose a graph neural network (GNN) model to achieve accurate and low-latency SAR ATR.
Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA
Compared with the state-of-the-art CNNs, the proposed GNN achieves comparable accuracy with $1/3258$ computation cost and $1/83$ model size.
Learning Practical Communication Strategies in Cooperative Multi-Agent Reinforcement Learning
In Multi-Agent Reinforcement Learning, communication is critical to encourage cooperation among agents.
Multi-agent Reinforcement Learning
reinforcement-learning
+1
Towards Programmable Memory Controller for Tensor Decomposition
Implementing accelerators on Field Programmable Gate Array (FPGA) for kernels such as MTTKRP is attractive due to the energy efficiency and the inherent parallelism of FPGA.
Model-Architecture Co-Design for High Performance Temporal GNN Inference on FPGA
Taking advantage of the model optimizations, we propose a principled hardware architecture using batching, pipelining, and prefetching techniques to further improve the performance.
Decoupling the Depth and Scope of Graph Neural Networks
We propose a design principle to decouple the depth and scope of GNNs -- to generate representation of a target entity (i. e., a node or an edge), we first extract a localized subgraph as the bounded-size scope, and then apply a GNN of arbitrary depth on top of the subgraph.
Ranked #3 on
Node Classification
on Reddit
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA
This paper focuses on a multi-faceted memory system, which explores the spatial and temporal locality of the data structures of MTTKRP.
SeDyT: A General Framework for Multi-Step Event Forecasting via Sequence Modeling on Dynamic Entity Embeddings
SeDyT consists of two components: a Temporal Graph Neural Network that generates dynamic entity embeddings in the past and a sequence model that predicts the entity embeddings in the future.
Programmable FPGA-based Memory Controller
Since developing memory controllers for different applications is time-consuming, this paper introduces a modular and programmable memory controller that can be configured for different target applications on available hardware resources.
Accelerating Large Scale Real-Time GNN Inference using Channel Pruning
In this paper, we propose to accelerate GNN inference by pruning the dimensions in each layer with negligible accuracy loss.
BRAC+: Going Deeper with Behavior Regularized Offline Reinforcement Learning
The goal of Offline Reinforcement Learning (RL) is to address this problem by learning effective policies using previously collected datasets.
Deep Graph Neural Networks with Shallow Subgraph Samplers
We propose a simple "deep GNN, shallow sampler" design principle to improve both the GNN accuracy and efficiency -- to generate representation of a target node, we use a deep GNN to pass messages only within a shallow, localized subgraph.
Accurate, Efficient and Scalable Training of Graph Neural Networks
For feature propagation within subgraphs, we improve cache utilization and reduce DRAM traffic by data partitioning.
GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms
We first analyze the computation and communication characteristics of various GCN training algorithms, and select a subgraph-based algorithm that is well suited for hardware execution.
SPEC2: SPECtral SParsE CNN Accelerator on FPGAs
On the other hand, weight pruning techniques address the redundancy in model parameters by converting dense convolutional kernels into sparse ones.
GraphSAINT: Graph Sampling Based Inductive Learning Method
Graph Convolutional Networks (GCNs) are powerful models for learning representations of attributed graphs.
Ranked #1 on
Link Property Prediction
on ogbl-citation2
Accurate, Efficient and Scalable Graph Embedding
However, a major challenge is to reduce the complexity of layered GCNs and make them parallelizable and scalable on very large graphs -- state-of the art techniques are unable to achieve scalability without losing accuracy and efficiency.
Accelerating PageRank using Partition-Centric Processing
The traditional PageRank implementation generates fine granularity random memory accesses resulting in large amount of wasteful DRAM traffic and poor bandwidth utilization.
Distributed, Parallel, and Cluster Computing Data Structures and Algorithms Performance
