Search Results for author: Harideep Nair

Found 7 papers, 2 papers with code

Realtime Person Identification via Gait Analysis

no code implementations2 Apr 2024 Shanmuga Venkatachalam, Harideep Nair, Prabhu Vellaisamy, Yongqi Zhou, Ziad Youssfi, John Paul Shen

In this paper, we propose a small CNN model with 4 layers that is very amenable for edge AI deployment and realtime gait recognition.

TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs

1 code implementation16 May 2022 Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen

Recent works have proposed a microarchitecture framework for implementing TNNs and demonstrated competitive performance on vision and time-series applications.

Time Series Time Series Clustering

A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks

no code implementations27 May 2021 Harideep Nair, John Paul Shen, James E. Smith

Temporal Neural Networks (TNNs) are spiking neural networks that use time as a resource to represent and process information, similar to the mammalian neocortex.

Continual Learning Incremental Learning

Unsupervised Clustering of Time Series Signals using Neuromorphic Energy-Efficient Temporal Neural Networks

no code implementations18 Feb 2021 Shreyas Chaudhari, Harideep Nair, José M. F. Moura, John Paul Shen

Unsupervised time series clustering is a challenging problem with diverse industrial applications such as anomaly detection, bio-wearables, etc.

Anomaly Detection Clustering +2

A Custom 7nm CMOS Standard Cell Library for Implementing TNN-based Neuromorphic Processors

no code implementations10 Dec 2020 Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen

A set of highly-optimized custom macro extensions is developed for a 7nm CMOS cell library for implementing Temporal Neural Networks (TNNs) that can mimic brain-like sensory processing with extreme energy efficiency.

Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing

no code implementations27 Aug 2020 Harideep Nair, John Paul Shen, James E. Smith

The TNN microarchitecture framework is embodied in a set of characteristic equations for assessing the total gate count, die area, compute time, and power consumption for any TNN design.

Hardware Aware Neural Network Architectures using FbNet

1 code implementation17 Jun 2019 Sai Vineeth Kalluru Srinivas, Harideep Nair, Vinay Vidyasagar

This will potentially enhance the ``hardware awareness" and help us find a neural network architecture that is optimal in terms of accuracy, latency and energy consumption, given a target device (Raspberry Pi in our case).

Benchmarking Neural Architecture Search

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