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Found 6 papers, 1 papers with code
UDC: Unified DNAS for Compressible TinyML Models
Deploying TinyML models on low-cost IoT hardware is very challenging, due to limited device memory capacity.
A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks
To attain accurate and efficient FCN models, we propose a three-step SW/HW co-design methodology consisting of FCN architectural exploration, precision quantization, and hardware acceleration.
Flexible Deep Neural Network Processing
In addition, DNNs are typically deployed in ensemble to boost accuracy performance, which further exacerbates the system requirements.
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks
In addition, we propose a hardware accelerator design to achieve low-power, low-latency inference with insignificant degradation in accuracy.
Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks
While a large number of dedicated hardware using different precisions has recently been proposed, there exists no comprehensive study of different bit precisions and arithmetic in both inputs and network parameters.
Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off
We present a novel dynamic configuration technique for deep neural networks that permits step-wise energy-accuracy trade-offs during runtime.
