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SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
Systolic array has emerged as a prominent architecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essential for deploying DNNs across diverse applications.
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators
In this paper, we propose an architecture of a novel adaptive fault-tolerant approximate multiplier tailored for ASIC-based DNN accelerators.
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
The stringent requirements for the Deep Neural Networks (DNNs) accelerator's reliability stand along with the need for reducing the computational burden on the hardware platforms, i. e. reducing the energy consumption and execution time as well as increasing the efficiency of DNN accelerators.
Enhancing Fault Resilience of QNNs by Selective Neuron Splitting
Thereafter, a novel method for splitting the critical neurons is proposed that enables the design of a Lightweight Correction Unit (LCU) in the accelerator without redesigning its computational part.
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors
Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in safety-critical applications raises new reliability concerns.
Special Session: Approximation and Fault Resiliency of DNN Accelerators
We propose to use approximate (AxC) arithmetic circuits to agilely emulate errors in hardware without performing fault injection on the DNN.
A Novel Fault-Tolerant Logic Style with Self-Checking Capability
We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level.
A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks
Through this SLR, three kinds of methods for reliability assessment of DNNs are identified including Fault Injection (FI), Analytical, and Hybrid methods.
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators
The framework enables selective approximation of reliability-critical DNNs, providing a set of Pareto-optimal DNN implementation design space points for the target resource utilization requirements.
DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment
In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons' outputs.
Unsupervised Recycled FPGA Detection Using Symmetry Analysis
Recently, recycled field-programmable gate arrays (FPGAs) pose a significant hardware security problem due to the proliferation of the semiconductor supply chain.
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors
In the preliminary phase of the work, the important goal is making a GCN which able to take a gate-level netlist as input information after transforming it into the Probabilistic Bayesian Graph in the form of Graph Modeling Language (GML).
