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AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly.
Mining SoC Message Flows with Attention Model
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs.
Deep Bidirectional Transformers for SoC Flow Specification Mining
High-quality system-level message flow specifications can lead to comprehensive validation of system-on-chip (SoC) designs.
Model Synthesis for Communication Traces of System-on-Chip Designs
In this paper, we consider the problem of inferring models from communication traces of system-on-chip~(SoC) designs.
