no code implementations • 15 Mar 2024 • Md Rubel Ahmed, Toshiaki Koike-Akino, Kieran Parsons, Ye Wang
High-level synthesis (HLS) is a design flow that leverages modern language features and flexibility, such as complex data structures, inheritance, templates, etc., to prototype hardware designs rapidly.
no code implementations • 12 Sep 2022 • Md Rubel Ahmed, Bardia Nadimi, Hao Zheng
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs.
no code implementations • 9 Mar 2022 • Md Rubel Ahmed, Hao Zheng
High-quality system-level message flow specifications can lead to comprehensive validation of system-on-chip (SoC) designs.
no code implementations • 13 Feb 2021 • Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
In this paper, we consider the problem of inferring models from communication traces of system-on-chip~(SoC) designs.