An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

4 May 2020Behzad SalamiErhan Baturay OnuralIsmail Emir YukselFahrettin KocOguz ErginAdrian Cristal KestelmanOsman S. UnsalHamid Sarbazi-AzadOnur Mutlu

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase... (read more)

PDF Abstract

Code


No code implementations yet. Submit your code now

Results from the Paper


  Submit results from this paper to get state-of-the-art GitHub badges and help the community compare results to other papers.

Methods used in the Paper


METHOD TYPE
🤖 No Methods Found Help the community by adding them if they're not listed; e.g. Deep Residual Learning for Image Recognition uses ResNet