Search Results for author:
Found 13 papers, 6 papers with code
Approximation Capabilities of Neural Networks using Morphological Perceptrons and Generalizations
Furthermore, we consider proposed signed-max-sum and max-star-sum generalizations of morphological ANNs and show that these variants also do not have universal approximation capabilities.
Improved Analysis of Current-Steering DACs Using Equivalent Timing Errors
Current-steering (CS) digital-to-analog converters (DACs) generate analog signals by combining weighted current sources.
Linearization for High-Speed Current-Steering DACs Using Neural Networks
This paper proposes a novel foreground linearization scheme for a high-speed CS-DAC.
Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning
In particular, we show the superiority of a greedy strategy and justify our choice of Bayesian optimization as the primary search methodology over random / grid search.
Pre-defined Sparsity for Low-Complexity Convolutional Neural Networks
We also compared the performance of our proposed architectures with that of ShuffleNet andMobileNetV2.
Neural Network Training with Approximate Logarithmic Computations
The high computational complexity associated with training deep neural networks limits online and real-time training on edge devices.
A Pre-defined Sparse Kernel Based Convolution for Deep CNNs
To explore the potential of this approach, we have experimented with two widely accepted datasets, CIFAR-10 and Tiny ImageNet, in sparse variants of both the ResNet18 and VGG16 architectures.
Pre-Defined Sparse Neural Networks with Hardware Acceleration
Neural networks have proven to be extremely powerful tools for modern artificial intelligence applications, but computational and storage complexity remain limiting factors.
A Highly Parallel FPGA Implementation of Sparse Neural Network Training
We demonstrate an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference.
Interleaver Design for Deep Neural Networks
We propose a class of interleavers for a novel deep neural network (DNN) architecture that uses algorithmically pre-determined, structured sparsity to significantly lower memory and computational requirements, and speed up training.
Characterizing Sparse Connectivity Patterns in Neural Networks
We propose a novel way of reducing the number of parameters in the storage-hungry fully connected layers of a neural network by using pre-defined sparsity, where the majority of connections are absent prior to starting training.
Accelerating Training of Deep Neural Networks via Sparse Edge Processing
We propose a reconfigurable hardware architecture for deep neural networks (DNNs) capable of online training and inference, which uses algorithmically pre-determined, structured sparsity to significantly lower memory and computational requirements.
