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Found 11 papers, 1 papers with code
Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements
First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS.
A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware
We propose an SDFG-based design flow for mapping spiking neural networks (SNNs) to many-core neuromorphic hardware with the objective of exploring the tradeoff between throughput and buffer size.
DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware
We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware.
Dynamic Reliability Management in Neuromorphic Computing
We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems, by designing an intelligent run-time manager (NCRTM), which dynamically destresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target.
NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks
Recently, both industry and academia have proposed many different neuromorphic architectures to execute applications that are designed with Spiking Neural Network (SNN).
Endurance-Aware Mapping of Spiking Neural Networks to Neuromorphic Hardware
We propose eSpine, a novel technique to improve lifetime by incorporating the endurance variation within each crossbar in mapping machine learning workloads, ensuring that synapses with higher activation are always implemented on memristors with higher endurance, and vice versa.
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition
With growing model complexity, mapping Spiking Neural Network (SNN)-based applications to tile-based neuromorphic hardware is becoming increasingly challenging.
Improving Dependability of Neuromorphic Computing With Non-Volatile Memory
We evaluate RENEU using different machine learning applications on a state-of-the-art neuromorphic hardware with NVM synapses.
Compiling Spiking Neural Networks to Neuromorphic Hardware
First, we propose a greedy technique to partition an SNN into clusters of neurons and synapses such that each cluster can fit on to the resources of a crossbar.
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing
Our framework first extracts the precise times at which a charge pump in the hardware is activated to support neural computations within a workload.
A New Approach to Dimensionality Reduction for Anomaly Detection in Data Traffic
This variance-based subspace approach to dimensionality reduction forces a fixed choice of the number of dimensions, is not responsive to real-time shifts in observed traffic patterns, and is vulnerable to normal traffic spoofing.
