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IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering For Versatile Video Coding
Image prefiltering with just noticeable distortion (JND) improves coding efficiency in a visual lossless way by filtering the perceptually redundant information prior to compression.
ASC: Adaptive Scale Feature Map Compression for Deep Neural Network
Furthermore, the hardware architecture scales effectively, with only a sublinear increase in area cost.
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator with Decoupled Asymmetric Convolution
This challenge leads many accelerators to opt for simpler and shallow models like FSRCNN, compromising performance for real-time needs, especially for resource-limited edge devices.
Real-Time Wearable Gait Phase Segmentation For Running And Walking
Previous gait phase detection as convolutional neural network (CNN) based classification task requires cumbersome manual setting of time delay or heavy overlapped sliding windows to accurately classify each phase under different test cases, which is not suitable for streaming Inertial-Measurement-Unit (IMU) sensor data and fails to adapt to different scenarios.
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization
Keyword spotting has gained popularity as a natural way to interact with consumer devices in recent years.
A Real Time Super Resolution Accelerator with Tilted Layer Fusion
Deep learning based superresolution achieves high-quality results, but its heavy computational workload, large buffer, and high external memory bandwidth inhibit its usage in mobile devices.
Row-wise Accelerator for Vision Transformer
Following the success of the natural language processing, the transformer for vision applications has attracted significant attention in recent years due to its excellent performance.
Hardware-Robust In-RRAM-Computing for Object Detection
However, in-RRAM computing (IRC) suffered from large device variation and numerous nonideal effects in hardware.
IMU Based Deep Stride Length Estimation With Self-Supervised Learning
The proposed model can achieve better average percent error, 4. 78\%, on running and walking stride length regression and 99. 83\% accuracy on running and walking classification, when compared to the previous approach, 7. 44\% on the stride length estimation.
Zebra: Memory Bandwidth Reduction for CNN Accelerators With Zero Block Regularization of Activation Maps
The large amount of memory bandwidth between local buffer and external DRAM has become the speedup bottleneck of CNN hardware accelerators, especially for activation maps.
Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model
Gait phase detection with convolution neural network provides accurate classification but demands high computational cost, which inhibits real time low power on-sensor processing.
BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention
Increasingly, convolution neural network (CNN) based super resolution models have been proposed for better reconstruction results, but their large model size and complicated structure inhibit their real-time hardware implementation.
Sparse Compressed Spiking Neural Network Accelerator for Object Detection
Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps.
PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting
Computing-in-memory (CIM) has attracted significant attentions in recent years due to its massive parallelism and low power consumption.
Pre-RTL DNN Hardware Evaluator With Fused Layer Support
With the popularity of the deep neural network (DNN), hardware accelerators are demanded for real time execution.
Efficient Accelerator for Dilated and Transposed Convolution with Decomposition
Hardware acceleration for dilated and transposed convolution enables real time execution of related tasks like segmentation, but current designs are specific for these convolutional types or suffer from complex control for reconfigurable designs.
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses because it significantly compromises the online training capability.
