Search Results for author: Tolulope A. Odetola

Found 8 papers, 0 papers with code

Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence

no code implementations18 Feb 2022 Adewale Adeyemo, Travis Sandefur, Tolulope A. Odetola, Syed Rafay Hasan

We further propose a library-based approach to design scalable and dynamic distributed CNN inference on the fly leveraging partial-reconfiguration techniques, which is particularly suitable for resource-constrained edge devices.

Security Analysis of Capsule Network Inference using Horizontal Collaboration

no code implementations22 Sep 2021 Adewale Adeyemo, Faiq Khalid, Tolulope A. Odetola, Syed Rafay Hasan

Similar to traditional CNNs, CapsNet is also vulnerable to several malicious attacks, as studied by several researchers in the literature.

Collaborative Inference Self-Driving Cars

Dynamic Distribution of Edge Intelligence at the Node Level for Internet of Things

no code implementations13 Jul 2021 Hawzhin Mohammed, Tolulope A. Odetola, Nan Guo, Syed Rafay Hasan

In this paper, dynamic deployment of Convolutional Neural Network (CNN) architecture is proposed utilizing only IoT-level devices.

SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN)

no code implementations16 Mar 2021 Tolulope A. Odetola, Syed Rafay Hasan

Security of inference phase deployment of Convolutional neural network (CNN) into resource constrained embedded systems (e. g. low end FPGAs) is a growing research area.

How Secure is Distributed Convolutional Neural Network on IoT Edge Devices?

no code implementations16 Jun 2020 Hawzhin Mohammed, Tolulope A. Odetola, Syed Rafay Hasan

The deployment of CNN on resource-constrained edge devices have proved challenging.

2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Deep Learning Architecture (DLA) onto FPGA Boards

no code implementations14 Nov 2019 Tolulope A. Odetola, Katie M. Groves, Syed Rafay Hasan

To the best of our knowledge this is the first work that proposes a 2-Level 3-Way (2L-3W) hardware-software co-verification methodology and provides a step-by-step guide for the successful mapping, deployment and verification of DLA on FPGA boards.

A Scalable Multilabel Classification to Deploy Deep Learning Architectures For Edge Devices

no code implementations5 Nov 2019 Tolulope A. Odetola, Ogheneuriri Oderhohwo, Syed Rafay Hasan

In this paper, we propose a methodology that solves this problem by extending the capability of existing multi-label classification and provide models with lower latency that requires smaller memory size when deployed on edge devices.

Classification General Classification +3

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