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Found 4 papers, 2 papers with code
HDLdebugger: Streamlining HDL debugging with Large Language Models
In the domain of chip design, Hardware Description Languages (HDLs) play a pivotal role.
IB-Net: Initial Branch Network for Variable Decision in Boolean Satisfiability
Boolean Satisfiability problems are vital components in Electronic Design Automation, particularly within the Logic Equivalence Checking process.
StoryAnalogy: Deriving Story-level Analogies from Large Language Models to Unlock Analogical Understanding
Analogy-making between narratives is crucial for human reasoning.
Self-Consistent Narrative Prompts on Abductive Natural Language Inference
However, the inter-sentential coherence and the model consistency have not been well exploited in the previous works on this task.
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