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Found 30 papers, 9 papers with code
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing
Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference.
Zero-shot Classification using Hyperdimensional Computing
Classification based on Zero-shot Learning (ZSL) is the ability of a model to classify inputs into novel classes on which the model has not previously seen any training examples.
Ranked #3 on
Zero-Shot Learning
on CUB-200-2011
Probabilistic Abduction for Visual Abstract Reasoning via Learning Rules in Vector-symbolic Architectures
Abstract reasoning is a cornerstone of human intelligence, and replicating it with artificial intelligence (AI) presents an ongoing challenge.
TCNCA: Temporal Convolution Network with Chunked Attention for Scalable Sequence Processing
We build upon their approach by replacing the linear recurrence with a special temporal convolutional network which permits larger receptive field size with shallower networks, and reduces the computational complexity to $O(L)$.
MIMONets: Multiple-Input-Multiple-Output Neural Networks Exploiting Computation in Superposition
MIMONets augment various deep neural network architectures with variable binding mechanisms to represent an arbitrary number of inputs in a compositional data structure via fixed-width distributed representations.
Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference
In this tutorial, we provide a deep dive into how such adaptations can be achieved and evaluated using the recently released IBM Analog Hardware Acceleration Kit (AIHWKit), freely available at https://github. com/IBM/aihwkit.
AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing
Digital processors based on typical von Neumann architectures are not conducive to edge AI given the large amounts of required data movement in and out of memory.
Factorizers for Distributed Sparse Block Codes
We provide a methodology to flexibly integrate our factorizer in the classification layer of CNNs with a novel loss function.
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators
Analog in-memory computing (AIMC) -- a promising approach for energy-efficient acceleration of deep learning workloads -- computes matrix-vector multiplications (MVMs) but only approximately, due to nonidealities that often are non-deterministic or nonlinear.
In-memory factorization of holographic perceptual representations
Disentanglement of constituent factors of a sensory signal is central to perception and cognition and hence is a critical task for future artificial intelligence systems.
Benchmarking energy consumption and latency for neuromorphic computing in condensed matter and particle physics
The massive use of artificial neural networks (ANNs), increasingly popular in many areas of scientific computing, rapidly increases the energy consumption of modern high-performance computing systems.
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory
We demonstrate for the first time how the EM unit can physically superpose multiple training examples, expand to accommodate unseen classes, and perform similarity search during inference, using operations on an IMC core based on phase-change memory (PCM).
Constrained Few-shot Class-incremental Learning
Moreover, it is imperative that such learning must respect certain memory and computational constraints such as (i) training samples are limited to only a few per class, (ii) the computational cost of learning a novel class remains constant, and (iii) the memory footprint of the model grows at most linearly with the number of classes observed.
Ranked #4 on
Few-Shot Class-Incremental Learning
on mini-Imagenet
continual few-shot learning
Few-Shot Class-Incremental Learning
+1
Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks
Memory-augmented neural networks enhance a neural network with an external key-value memory whose complexity is typically dominated by the number of support vectors in the key memory.
A Neuro-vector-symbolic Architecture for Solving Raven's Progressive Matrices
Compared to state-of-the-art deep neural network and neuro-symbolic approaches, end-to-end training of NVSA achieves a new record of 87. 7% average accuracy in RAVEN, and 88. 1% in I-RAVEN datasets.
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator
We also describe AON-CiM, a programmable, minimal-area phase-change memory (PCM) analog CiM accelerator, with a novel layer-serial approach to remove the cost of complex interconnects associated with a fully-pipelined design.
A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays
We introduce the IBM Analog Hardware Acceleration Kit, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PyTorch (freely available at https://github. com/IBM/aihwkit).
Robust High-dimensional Memory-augmented Neural Networks
Traditional neural networks require enormous amounts of data to build their complex mappings during a slow training procedure that hinders their abilities for relearning and adapting to new data.
Few-Shot Image Classification
Vocal Bursts Intensity Prediction
Optimality of short-term synaptic plasticity in modelling certain dynamic environments
Biological neurons and their in-silico emulations for neuromorphic artificial intelligence (AI) use extraordinarily energy-efficient mechanisms, such as spike-based communication and local synaptic plasticity.
Memristors -- from In-memory computing, Deep Learning Acceleration, Spiking Neural Networks, to the Future of Neuromorphic and Bio-inspired Computing
Machine learning, particularly in the form of deep learning, has driven most of the recent fundamental developments in artificial intelligence.
File Classification Based on Spiking Neural Networks
In this paper, we propose a system for file classification in large data sets based on spiking neural networks (SNNs).
ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning
Strategies to improve the efficiency of MVM computation in hardware have been demonstrated with minimal impact on training accuracy.
Compiling Neural Networks for a Computational Memory Accelerator
Computational memory (CM) is a promising approach for accelerating inference on neural networks (NN) by using enhanced memories that, in addition to storing data, allow computations on them.
5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory
We show that this communication fabric facilitates the pipelined execution of all state of-the-art CNNs by proving the existence of a homomorphism between one graph representation of these networks and the proposed graph topology.
Accurate deep neural network inference using computational phase-change memory
In-memory computing is a promising non-von Neumann approach where certain computational tasks are performed within memory units by exploiting the physical attributes of memory devices.
Emerging Technologies
In-memory hyperdimensional computing
Hyperdimensional computing (HDC) is an emerging computational framework that takes inspiration from attributes of neuronal circuits such as hyperdimensionality, fully distributed holographic representation, and (pseudo)randomness.
Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses
Combining the computational potential of supervised SNNs with the parallel compute power of computational memory, the work paves the way for next-generation of efficient brain-inspired systems.
Low-Power Neuromorphic Hardware for Signal Processing Applications
In this paper, we review some of the architectural and system level design aspects involved in developing a new class of brain-inspired information processing engines that mimic the time-based information encoding and processing aspects of the brain.
Fatiguing STDP: Learning from Spike-Timing Codes in the Presence of Rate Codes
However, some spike-timing-related strengths of SNNs are hindered by the sensitivity of spike-timing-dependent plasticity (STDP) rules to input spike rates, as fine temporal correlations may be obstructed by coarser correlations between firing rates.
Mixed-Precision In-Memory Computing
As CMOS scaling reaches its technological limits, a radical departure from traditional von Neumann systems, which involve separate processing and memory units, is needed in order to significantly extend the performance of today's computers.
Emerging Technologies
