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Found 8 papers, 2 papers with code
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency.
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations using Boolean logic gates.
Towards the Imagenets of ML4EDA
Here we describe our experience curating two large-scale, high-quality datasets for Verilog code generation and logic synthesis.
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
%Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks.
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Oracle-less machine learning (ML) attacks have broken various logic locking schemes.
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Generating sub-optimal synthesis transformation sequences ("synthesis recipe") is an important problem in logic synthesis.
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design.
Adversarially Robust Learning via Entropic Regularization
In this paper we propose a new family of algorithms, ATENT, for training adversarially robust deep neural networks.
