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Found 13 papers, 1 papers with code
EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration
In this new design, the multipliers are replaced by simple logic gates to project the results onto a wide bit representation.
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation
In conventional ONNs, light amplitudes are modulated at the input and detected at the output.
Logic Design of Neural Networks for High-Throughput and Low-Power Applications
However, under a given area constraint, the number of MAC units in such platforms is limited, so MAC units have to be reused to perform MAC operations in a neural network.
MLonMCU: TinyML Benchmarking with Fast Retargeting
Thus, automating the end-to-end benchmarking flow is of high relevance nowadays.
Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks
Deep neural networks (DNNs) have been widely deployed across diverse domains such as computer vision and natural language processing.
Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference
It improves TinyML memory optimization significantly by reducing memory of models where this was not possible before and additionally providing alternative design points for models that show high run time overhead with existing methods.
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration
To address this challenge, we propose PowerPruning, a novel method to reduce power consumption in digital neural network accelerators by selecting weights that lead to less power consumption in MAC operations.
Biologically Plausible Learning on Neuromorphic Hardware Architectures
Using the benchmarking framework DNN+NeuroSim, we investigate the impact of hardware nonidealities and quantization on algorithm performance, as well as how network topologies and algorithm-level design choices can scale latency, energy and area consumption of a chip.
Class-based Quantization for Neural Networks
In the proposed method, the importance score of each filter or neuron with respect to the number of classes in the dataset is first evaluated.
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement
In such platforms, neural networks need to provide acceptable results quickly and the accuracy of the results should be able to be enhanced dynamically according to the computational resources available in the computing system.
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation
These acceleration platforms rely on analog properties of the devices and thus suffer from process variations and noise.
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
As the relative power, performance, and area (PPA) impact of embedded memories continues to grow, proper parameterization of each of the thousands of memories on a chip is essential.
Predicting Memory Compiler Performance Outputs using Feed-Forward Neural Networks
A key task in the design flow of a chip is to find optimal memory compiler parametrizations which on the one hand fulfill system requirements while on the other hand optimize PPA.
