Search Results for author: Vivek Sarkar

Found 8 papers, 2 papers with code

Task-Graph Scheduling Extensions for Efficient Synchronization and Communication

no code implementations6 Nov 2020 Seonmyeong Bak, Oscar Hernandez, Mark Gates, Piotr Luszczek, Vivek Sarkar

Task graphs have been studied for decades as a foundation for scheduling irregular parallel applications and incorporated in programming models such as OpenMP.

Distributed, Parallel, and Cluster Computing

Advanced Graph-Based Deep Learning for Probabilistic Type Inference

1 code implementation13 Sep 2020 Fangke Ye, Jisheng Zhao, Vivek Sarkar

As a result, there is a strong motivation for new approaches that can advance the state of the art in statically predicting types in dynamically typed programs, and that do so with acceptable performance for use in interactive programming environments.

Vocal Bursts Type Prediction

Context-Aware Parse Trees

no code implementations24 Mar 2020 Fangke Ye, Shengtian Zhou, Anand Venkat, Ryan Marcus, Paul Petersen, Jesmin Jahan Tithi, Tim Mattson, Tim Kraska, Pradeep Dubey, Vivek Sarkar, Justin Gottschlich

The simplified parse tree (SPT) presented in Aroma, a state-of-the-art code recommendation system, is a tree-structured representation used to infer code semantics by capturing program \emph{structure} rather than program \emph{syntax}.

Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators

no code implementations18 Feb 2020 Prasanth Chatarasi, Hyoukjun Kwon, Natesh Raina, Saurabh Malik, Vaisakh Haridas, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar

Searching for the optimal mappings is challenging because of the large space of mappings, and this challenge gets exacerbated with new operators and diverse accelerator configurations. To address this challenge, we propose a decoupled off-chip/on-chip approach that decomposes the mapping space into off-chip and on-chip subspaces, and first optimizes the off-chip subspace followed by the on-chip subspace.

Topkapi: Parallel and Fast Sketches for Finding Top-K Frequent Elements

1 code implementation NeurIPS 2018 Ankush Mandal, He Jiang, Anshumali Shrivastava, Vivek Sarkar

In particular, for identifying top-K frequent items, Count-Min Sketch (CMS) has fantastic update time but lack the important property of reducibility which is needed for exploiting available massive data parallelism.

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO

no code implementations4 May 2018 Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna

The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, and they directly impact the performance and energy efficiency of DNN accelerator designs.

Scheduling valid

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